Stacked Memory Core Dies Wafer-Level Test Control
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Solution Overview
Problem
Current stacked memory devices face challenges in performing wafer-level tests due to the complexity of the structure, where most address/command control circuits are disposed in the base die, making it difficult to conduct thorough tests on each core die without increasing the number of through-silicon vias (TSVs) and occupying more area.
Innovation Solution
Each core die in the stacked memory device generates equivalent global control signals corresponding to those generated by the base die, allowing for selection based on whether a package-level or wafer-level test is performed, enabling efficient wafer-level testing by redistributing test mode signals and addresses through TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If most address/command control circuits are disposed in the base die, then the device complexity is reduced, but the ability to perform wafer-level tests on core dies is compromised
Solution Approach 1:
The patent segments the control circuit functionality by distributing address/command control circuits to each core die while maintaining a base die. This segmentation enables independent wafer-level testing of core dies without requiring complex interconnections, as each core die has the necessary control circuits locally available.
Solution Approach 2:
The patent introduces an intermediary mechanism where the base die coordinates testing activities while core dies perform autonomous control functions during wafer-level tests. This intermediary role allows the base die to manage the testing process without requiring full control circuit duplication, balancing complexity and test capability.
2Reliability
If additional TSVs are added to support wafer-level testing, then the test capability is improved, but the area occupation increases
Solution Approach 1:
The patent applies preliminary action by equipping each core die with address/command control circuits before the stacking process. This preliminary configuration enables wafer-level testing to be performed on core dies independently before assembly, eliminating the need for additional TSVs that would be required if testing were performed only after stacking.
Solution Approach 2:
Each core die is designed to be self-sufficient for wafer-level testing by incorporating the necessary address/command control circuits locally. This self-service capability allows core dies to undergo comprehensive testing without requiring additional external connections or TSVs, thereby minimizing area occupation.
3Adaptability or versatility
If more input pads are provided on core dies, then the test flexibility is improved, but the device complexity increases
Solution Approach 1:
The patent implements universality by designing input pads on core dies that can serve multiple functions: receiving addresses during wafer-level tests, receiving commands during package-level tests, and maintaining compatibility with standard memory operations. This multi-functionality provides test flexibility without requiring separate dedicated pads for each test mode, thereby avoiding increased device complexity.
Solution Approach 2:
The patent applies dynamics by enabling input pads to dynamically switch between different test modes (wafer-level and package-level) based on the testing requirements. This dynamic configurability allows the same input pads to adapt to different test scenarios, providing versatility without the need for additional static input pads that would increase device complexity.
Data Source
AI summary
Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.