Stacked Memory-CPU Architecture for Low Power High Speed Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor storage devices like DRAMs, SRAMs, and NAND universal memories face challenges in high-speed data transmission due to long wiring distances, high power consumption, and differing fabrication processes, making it difficult to connect them efficiently with CPUs and switch data writing and reading speeds effectively.
Innovation Solution
An information processing device with a layered structure incorporating a NAND semiconductor storage device and a CPU connected through short wiring, utilizing metal oxide transistors for low off-state current and multilevel data retention, and an accelerator for neural network inference processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If semiconductor storage devices are connected to CPUs through long wiring distances, then data transmission can be achieved, but power consumption increases and transmission speed decreases
Solution Approach 1:
The patent combines the semiconductor storage device and CPU into a single integrated chip structure, eliminating the need for long external wiring connections. This merging of previously separate components directly reduces power consumption and increases data transmission speed by minimizing the physical distance between storage and processing units.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture, where the storage device is positioned vertically above the CPU. This dimensional change enables shorter wiring paths through vertical interconnects, simultaneously reducing power consumption and improving data transmission speed.
2Reliability
If NAND universal memory is used for storage, then nonvolatile data retention is achieved, but fabrication process compatibility with cache memory becomes difficult
Solution Approach 1:
The patent develops a unified fabrication process that can manufacture both NAND universal memory cells and cache memory cells (DRAM or SRAM) using the same manufacturing steps and materials. This universal fabrication approach enables both nonvolatile data retention from NAND and high-speed caching functionality to coexist on the same chip without requiring separate production lines.
3Productivity
If separate fabrication processes are used for storage devices and CPUs, then specialized optimization is achieved, but device complexity and connection difficulties increase
Solution Approach 1:
The patent merges the fabrication processes for storage devices and CPUs into a single integrated process flow, eliminating the need for separate manufacturing operations. This consolidation reduces device complexity while maintaining the specialized optimization needed for high productivity in both storage and processing functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced power consumption, high-speed data transfer, and efficient switching of data writing and reading speeds in NAND semiconductor storage devices, while allowing for compact and reliable operation.
Implementation Method 1
The OS transistor has a feature of an extremely low drain current in an off state (the current is also referred to as an off-state current)
Data Source
AI summary
A novel information processing device with least signal transmission delay and low power consumption is provided. A storage device includes a first layer, a second layer, and a third layer. The first layer is provided with a circuit. The second layer is provided with a memory cell portion. The third layer is provided with a first electrode. The circuit has a function of switching and performing reading or writing of first data or second data from or to the memory cell portion. At least part of the second layer is stacked above the first layer. At least part of the third layer is stacked above the second layer. An arithmetic device includes a fourth layer and a fifth layer. The fourth layer is provided with a central processing device. The fifth layer is provided with a second electrode. At least part of the fifth layer is stacked above the fourth layer. The circuit is electrically connected to the central processing device through the first electrode and the second electrode.