Stacked Memory Chip Structure for Crack Containment During Bonding
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in preventing cracking and distortion during the manufacturing process, particularly when bonding array and circuit chips, which can lead to defective chips due to unintended cracking along material interfaces.
Innovation Solution
The semiconductor storage device incorporates a second substrate with strategically formed openings and a partition wall to redirect and contain cracking, preventing its transfer to critical storage or control regions by guiding it in the Z direction, thereby enhancing the structural integrity and reducing the likelihood of chip defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If array and circuit chips are bonded together to form semiconductor storage device, then device functionality is achieved, but cracking and distortion occur during manufacturing process
Solution Approach 1:
A buffer layer is introduced between the array chip and circuit chip to act as an intermediary that absorbs thermal expansion differences and mechanical stress during bonding. This buffer layer prevents direct stress transmission that causes cracking at material interfaces, thereby maintaining bonding reliability while eliminating the harmful cracking effect.
Solution Approach 2:
The patent applies beforehand cushioning by pre-forming a recess structure in the substrate before bonding the chips. This recess accommodates potential cracking and distortion by providing a cushioning space that prevents cracks from propagating into critical circuit regions, thus protecting the device functionality while managing the inherent cracking risk during bonding.
2Adaptability or versatility
If chips are bonded to achieve storage device functionality, then device operation is enabled, but unintended cracking occurs along material interfaces
Solution Approach 1:
The buffer layer serves as a mediator between dissimilar materials (array chip and circuit chip substrates), enabling their bonding while preventing interface cracking. This intermediary layer allows the device to achieve full functionality by facilitating the bonding process without compromising manufacturing precision, as it suppresses crack formation at the critical material interface.
Solution Approach 2:
The patent applies local quality by creating a recess structure specifically at the bonding interface region where cracking is most likely to occur. This localized structural modification provides crack accommodation only where needed, allowing the rest of the device to maintain high manufacturing precision while enabling device functionality through successful chip bonding.
3Ease of manufacture
If conventional bonding process is used, then manufacturing simplicity is maintained, but defective chips result due to cracking transfer to critical regions
Solution Approach 1:
The recess structure is formed beforehand in the substrate before chip bonding, creating a cushioning zone that captures and contains any cracking that occurs during the bonding process. This approach maintains the simplicity of the bonding process itself while dramatically reducing defective chip rate by preventing cracks from reaching critical circuit regions through the cushioning effect of the recess.
Solution Approach 2:
The buffer layer acts as an intermediary that absorbs bonding-induced stress and prevents crack propagation to critical regions. This allows the use of conventional simple bonding processes without incurring high defective chip rates, as the buffer layer mediates the stress distribution and protects vulnerable areas from cracking.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first chip and a second chip. The first chip includes a first substrate, a transistor, and a first pad. The second chip includes a second pad, a memory cell array, and a second substrate. The second pad is on the first pad. The second chip is bonded to the first chip. The first chip and the second chip includes, when viewed in a first direction orthogonal to the first substrate, a first region and a second region. The first region includes the memory cell array. The second region surrounds an area around the first region and includes a wall extending from the first substrate to the second substrate. The second substrate includes a first opening passing through the second substrate in the second region.