Stacked Semiconductor Memory Device Crack Prevention
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Solution Overview
Problem
Miniaturized semiconductor memory cards with high capacity face challenges in preventing cracks during resin sealing due to surface irregularities on the wiring board, particularly affecting the bottom memory element in multilayered configurations.
Innovation Solution
A semiconductor memory device design where the first semiconductor memory element has a greater thickness than the second, with a spacer layer in between to prevent contact and cracking, and the controller element is stacked on the second memory element, ensuring the first memory element absorbs local pressure during sealing, while the second memory element is kept thinner to maintain card thickness and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of memory elements is decreased to enable multilayer stacking for high capacity, then the storage capacity increases, but the memory elements become prone to cracking during mold forming due to surface irregularities
Solution Approach 1:
The patent applies different thickness specifications to different memory elements in the stack. The first memory element (bottom layer) is specified to have a thickness of 50-150 μm, while the second memory element (upper layer) has a thickness of 10-50 μm. This local differentiation allows the bottom element to absorb molding stress while maintaining overall device thinness for high capacity.
2Quantity of substance
If multiple memory elements are stacked to increase storage capacity, then the capacity increases, but the total thickness increases, conflicting with miniaturization requirements
Solution Approach 1:
The patent transitions from increasing capacity through lateral expansion to vertical stacking in the thickness dimension. By stacking multiple memory elements (first and second memory elements) vertically on the wiring board, the design achieves high capacity while maintaining a compact card form factor suitable for miniaturized memory cards.
3Reliability
If the first memory element is made thicker to prevent cracking during mold forming, then the reliability improves, but the total stacked thickness increases
Solution Approach 1:
The patent optimizes the thickness parameters of individual memory elements within specific ranges. The first memory element is set to 50-150 μm and the second to 10-50 μm, creating a parameter distribution that balances crack resistance with overall thinness. This parameter optimization allows the bottom element to serve as a stress-absorbing foundation while keeping the total stack thickness minimal.
Data Source
AI summary
A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.