Cross-Layer Repair in Stacked Semiconductor Memory Devices
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Solution Overview
Problem
Existing semiconductor memory devices with three-dimensional chip integration technology cannot effectively repair memory chips across different layers, leading to a lower yield due to the inability to utilize redundant memory blocks for cross-layer repairs.
Innovation Solution
A repairable semiconductor memory device is designed with an input/output bus and multiple memory chips stacked together, along with a redundant repair unit. Each memory chip and the redundant repair unit compare memory address information with address to be repaired information to determine whether to allow data access or redirect it to redundant memory cells, enabling cross-layer repairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory chip uses its own redundant memory blocks for repair, then the repair mechanism is simple and self-contained, but memory chips in other layers cannot be repaired, leading to lower device yield
Solution Approach 1:
The patent merges the redundant memory blocks from multiple memory chips into a single shared redundant memory array that can serve any layer. The repair control unit coordinates access to this unified redundant resource, enabling cross-layer repair while maintaining manageable system complexity through centralized control.
Solution Approach 2:
The shared redundant memory array is designed with universal functionality to repair memory cells in any layer, not just the local layer. The repair control unit manages this universal resource by identifying which memory chip needs repair and directing the appropriate redundant memory cells accordingly, making the redundant memory blocks multi-functional across layers.
2Reliability
If redundant memory blocks are shared across layers, then cross-layer repair is enabled and device yield improves, but the control and coordination complexity increases
Solution Approach 1:
The repair control unit acts as an intermediary between the memory chips and the shared redundant memory array. It receives repair requests from any layer, identifies the source memory chip, and coordinates access to the appropriate redundant memory cells, simplifying the operation complexity through a dedicated control mechanism.
Solution Approach 2:
The system implements feedback mechanisms where the repair control unit monitors the repair process and coordinates access to redundant memory blocks. This feedback loop ensures proper allocation and prevents conflicts when multiple layers need repair simultaneously, making the complex shared resource management tractable.
Data Source
AI summary
A repairable semiconductor memory device includes an input/output bus, a plurality of stacked memory chips, and a redundant repair unit. Each of the memory chips compares a memory address information with an address information to be repaired to generate a first comparison result for determining whether to allow the input/output bus to access the data corresponding to the memory address information in the memory chips. The redundancy repair unit compares the memory address information with the address information to be repaired to generate a second comparison result for determining whether to allow a redundant memory cell corresponding to the memory address information to be coupled to the input/output bus. In this way, the semiconductor memory device can repair any layer of the memory chips to improve the yield to solve the problem of previously having a lower yield.