Stacked Memory Deck Layout for Compact Cross-Point Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in reducing chip size while maintaining performance and efficiency, particularly in the design of cross-point memory devices with variable resistance memory cells, where the size difference between NMOS and PMOS transistors affects the overall area occupancy.
Innovation Solution
The memory device incorporates a stacked structure with alternating layers of NMOS and PMOS transistors, where even-numbered and odd-numbered connection structures are strategically positioned to reduce the area occupied by select components, allowing for a more compact layout by sharing column lines and optimizing the arrangement of memory cells and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NMOS and PMOS transistors are used in cross-point memory devices, then select functionality is improved, but area occupancy increases due to size difference between transistor types
Solution Approach 1:
The patent merges NMOS and PMOS transistors into a stacked configuration where they share common structures and spacing. The even-numbered and odd-numbered connection structures are interleaved vertically, allowing both transistor types to coexist in a compact arrangement that reduces total area occupancy while maintaining their distinct select functionalities.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked structure. Connection structures are arranged in alternating even and odd positions along the vertical direction, utilizing the third dimension to reduce footprint area. This vertical stacking allows NMOS and PMOS transistors to be positioned at different heights while sharing common bit lines and spacing structures.
2Quantity of substance
If more memory cells are integrated to increase capacity, then storage capability is improved, but chip size increases
Solution Approach 1:
The patent implements a three-dimensional stacked memory architecture where multiple decks of memory cells are arranged vertically along the vertical direction. This allows significant increase in storage capacity by utilizing vertical space rather than expanding chip footprint horizontally, effectively integrating more memory cells without proportionally increasing chip size.
Solution Approach 2:
The patent employs shared column lines that serve multiple decks of memory cells simultaneously. The even-numbered and odd-numbered connection structures share common bit lines and spacing structures, allowing a single column line to access memory cells across multiple vertical levels, thereby increasing capacity without linearly increasing the number of required interconnect structures.
3Area of stationary object
If connection structures are densely arranged to reduce spacing, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the connection structures into alternating even-numbered and odd-numbered groups positioned at different vertical levels. This segmentation creates distinct manufacturing zones with standardized spacing patterns, making it easier to control precision during fabrication. Each deck can be manufactured with consistent spacing requirements rather than requiring progressively tighter spacing across the entire structure.
Solution Approach 2:
By arranging connection structures in alternating even and odd positions along the vertical direction rather than compressing them horizontally, the patent maintains adequate spacing between structures while improving area efficiency through vertical utilization. This dimensional transition preserves manufacturability by avoiding excessive lateral crowding that would demand ultra-precise alignment.
Data Source
AI summary
A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.