Stacked Memory Layout Separating CuA Array and Peripheral Circuits
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Solution Overview
Problem
Existing stacked memory devices face challenges in improving access rate due to the limitations of the CMOS-under-array (CuA) process, which damages advanced process materials and structures with high thermal budgets.
Innovation Solution
The memory device is structured with peripheral circuits on a first chip and a stack memory cell array with a first address circuit on a second chip, allowing the second chip to undergo the CuA process while the first chip uses a process with a relatively low thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the CMOS-under-array (CuA) process is used to stack the memory cell array, then the area on the chip is conserved, but the thermal budget damages advanced process materials and structures in peripheral circuits
Solution Approach 1:
The memory device is divided into two separate chips: a first chip containing peripheral circuits and a second chip containing the stack memory cell array. This segmentation allows each chip to undergo appropriate manufacturing processes independently, enabling the second chip to receive the full thermal budget of the CuA process while the first chip avoids thermal damage to its advanced process materials and structures.
2Productivity
If the stacking level of the memory cell array is increased to improve memory capacity, then the access rate must also be increased, but advanced process materials for high-speed peripheral circuits cannot be applied due to thermal budget constraints
Solution Approach 1:
By separating peripheral circuits and memory cell array onto different chips, the invention enables the peripheral circuits to be manufactured using advanced process materials and structures optimized for high-speed operation, while the memory cell array undergoes the CuA process. This resolves the contradiction by allowing high-speed peripheral circuits to achieve improved access rates without being constrained by thermal budget limitations.
Data Source
AI summary
A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.