Stacked Semiconductor Memory Bank Group Data Path Selector
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Solution Overview
Problem
Semiconductor memory devices with stacked structures face challenges in optimizing data paths and reducing line loading of global input/output lines, leading to increased area requirements and line loading issues due to shared global input/output lines across banks.
Innovation Solution
A semiconductor memory device with a stacked structure that includes a data path selector to electrically connect specific bank groups through chip vias, allowing for selective data transfer between upper and lower bank groups, thereby reducing the number of global input/output lines and chip through vias, and optimizing data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If global input/output lines are shared across multiple banks, then device area is reduced, but line loading increases
Solution Approach 1:
The patent divides the banks into first and second bank groups, where the first bank group shares first global input/output lines and the second bank group shares second global input/output lines. This segmentation reduces line loading by isolating data paths for different bank groups, preventing signal interference while maintaining compact device area.
2Reliability
If chip through vias are used to connect stacked chips, then vertical electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent implements a stacked package structure where multiple semiconductor chips are vertically stacked and connected through chip through vias. The first semiconductor chip includes first pad groups connected to first global input/output lines, and the second semiconductor chip includes second pad groups connected to second global input/output lines, creating a nested vertical interconnection architecture that achieves reliable electrical connections while managing manufacturing complexity through systematic via placement.
3Speed
If data path is optimized by selecting specific bank groups, then data transition time is reduced, but control complexity increases
Solution Approach 1:
The patent introduces a data path selector that dynamically switches between different data paths based on operational requirements. The selector can connect to either the first global input/output lines or the second global input/output lines, allowing flexible data path configuration to optimize data transition times while managing control complexity through selective switching rather than fixed complex routing.
Data Source
AI summary
A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via.