Stacked Memory Cell Layout for Low-Power Data Retention
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing area occupation, power consumption, and data retention time, with volatile memory devices requiring frequent refresh and high power consumption, while non-volatile devices struggle with speed and insulating film degradation.
Innovation Solution
A semiconductor device comprising a first transistor, a second transistor, and a capacitor, where data is written by accumulating electric charge in the capacitor through the second transistor and held by turning off the second transistor, with the second transistor and capacitor overlapping the first transistor, allowing for low-power operation and reduced area usage, utilizing a wide band gap oxide semiconductor for the second transistor to minimize off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a DRAM memory element is used to reduce area, then area is reduced, but data retention period becomes extremely short requiring frequent refresh operations
Solution Approach 1:
The patent uses a composite structure combining a transistor with a capacitor stacked over it, where the capacitor provides long-term data retention and the transistor enables low-power operation. This composite approach resolves the contradiction by integrating the area benefits of DRAM with the retention benefits of non-volatile memory structures.
Solution Approach 2:
The patent transitions from planar DRAM structure to a three-dimensional stacked structure where the capacitor is positioned over the transistor. This vertical stacking in another dimension allows the memory element to achieve both small area footprint and long data retention period simultaneously.
2Speed
If an SRAM is used to operate at high speed, then speed is improved, but area becomes large due to multiple transistors
Solution Approach 1:
The patent extracts the essential function of SRAM (high-speed operation) while removing the unnecessary complexity of multiple transistors. By using a single transistor with a stacked capacitor, the design achieves high speed operation with minimal area, resolving the contradiction between speed and area.
3Duration of action of stationary object
If flash memory is used to hold data without power, then data retention is improved, but power consumption increases due to high voltage requirements
Solution Approach 1:
The patent changes the operating parameters by using a transistor with a stacked capacitor that requires low voltage for data retention, unlike flash memory that requires high voltage. This parameter change enables long-term data retention without the high power consumption associated with flash memory's high voltage operations.
4Area of stationary object
If transistor size is miniaturized to increase integration, then area is reduced, but off-state current increases leading to higher power consumption
Solution Approach 1:
The patent employs a composite structure where the transistor is combined with a capacitor in a stacked configuration. This composite design allows the use of miniaturized transistors while maintaining low power consumption, as the capacitor stores charge and reduces the need for continuous current to maintain state.
Solution Approach 2:
The capacitor acts as an intermediary between the transistor and the data storage function. It mediates the contradiction by storing charge and reducing the transistor's off-state current impact, allowing miniaturization without proportional increase in power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a semiconductor device with reduced area, low power consumption, and extended data retention even after power is stopped, achieving high integration and efficient data storage.
Implementation Method 1
a transistor formed using an oxide semiconductor with a wide band gap has significantly high off-state resistance
Data Source
AI summary
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.