Thin-Film Deck Selection Using Shared Column Decoders in Stacked Memory
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Solution Overview
Problem
As memory devices scale, the area of the substrate required for decoding and addressing circuitry increases, limiting the number of decks that can be supported due to space constraints, leading to inefficiencies in memory array access and operation.
Innovation Solution
Implementing thin film transistor deck selection by distributing deck selection components among the layers of a memory device, using vertical transistors and shared column decoders to access memory arrays, thereby moving decoding circuitry above the substrate and optimizing substrate area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If decoding and addressing circuitry is implemented on the substrate, then memory device functionality is achieved, but substrate area is consumed limiting the number of supported decks
Solution Approach 1:
The patent moves decoding and addressing circuitry from the substrate plane to the vertical dimension by implementing them on memory decks above the substrate. This dimensional transition allows the substrate to be dedicated entirely to memory arrays while decoding circuitry occupies vertical space, thereby increasing the number of supported decks without consuming additional substrate area.
2Quantity of substance
If more decks are supported, then memory capacity increases, but substrate area for decoding circuitry becomes insufficient
Solution Approach 1:
The patent resolves the space constraint by transitioning decoding circuitry to the vertical dimension on memory decks. This allows memory capacity to scale with the number of decks without being limited by substrate area, as decoding resources are distributed vertically rather than competing for horizontal substrate space.
Solution Approach 2:
The patent segments decoding and addressing circuitry into distributed components located on individual memory decks. Each deck contains its own decoding resources, allowing parallel operation and eliminating the need for a centralized large-area decoder on the substrate, thereby supporting more decks within the same substrate footprint.
3Ease of operation
If decoding circuitry is centralized on the substrate, then addressing is simplified, but substrate area utilization becomes inefficient
Solution Approach 1:
The patent segments the centralized decoding function into distributed decoding units on each memory deck. While this adds some complexity to the addressing architecture, it dramatically improves substrate area utilization by eliminating the need for a large centralized decoder, allowing the substrate to be fully utilized for high-density memory arrays.
Data Source
AI summary
Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.