Stacked Memory Cell Decks With Pillars for Scalable Conductive Paths
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Solution Overview
Problem
Conventional techniques face challenges in forming conductive paths and structures to accommodate a large number of stacked memory cells, limiting the number of decks in memory devices and thus memory cell density.
Innovation Solution
The memory device employs decks of memory cells stacked over a semiconductor substrate with pillars and scalable conductive paths coupled to control gates, allowing for a higher number of decks and increased memory cell density without structural limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional techniques are used to form conductive paths and structures, then the manufacturing process is simpler, but the number of stacked memory cell levels is limited
Solution Approach 1:
The memory device is divided into multiple decks, with each deck containing a subset of memory cells and control gates. This segmentation allows the conductive paths to be organized in manageable groups rather than requiring continuous paths through all levels, thereby enabling more stacked levels while controlling the complexity of individual conductive path structures.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked architecture with multiple decks arranged vertically. By utilizing the vertical dimension and stacking decks one over another, the device achieves higher memory cell density and more stacked levels without proportionally increasing the complexity of conductive paths within each deck.
2Quantity of substance
If a large number of stacked memory cells are implemented, then memory cell density increases, but forming conductive paths becomes difficult or unachievable
Solution Approach 1:
By dividing the memory device into multiple decks where each deck contains a portion of the memory cells and associated control gates, the conductive paths within each deck remain manageable in length and complexity. This segmentation enables high overall memory cell density while keeping individual conductive path formation feasible through standard manufacturing processes.
Solution Approach 2:
The conductive paths are formed within each deck before stacking the decks together. This preliminary formation of conductive paths in smaller, manageable units simplifies the manufacturing process compared to attempting to form continuous conductive paths through all stacked levels simultaneously, thereby enabling higher memory cell density.
3Quantity of substance
If more decks are stacked, then storage capacity increases, but structural limitations are imposed
Solution Approach 1:
The patent utilizes vertical stacking of multiple decks in the third dimension to increase storage capacity without proportionally increasing the horizontal footprint or structural complexity within each deck. Each deck is a self-contained unit that can be replicated and stacked, allowing scalable storage capacity while maintaining manageable structural complexity at each level.
Solution Approach 2:
By segmenting the memory device into identical or similar deck units that can be stacked, the structural complexity is standardized and replicated rather than continuously increasing. Each deck contains a manageable subset of memory cells and control gates with associated conductive paths, allowing multiple decks to be stacked to increase storage capacity while maintaining consistent, manageable structural complexity throughout.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.