Stacked Memory Die Trim Circuits for Signal Delay Alignment
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Solution Overview
Problem
As memory densities increase, stacked memory devices face challenges with signal alignment and timing issues due to internal connection delays and CMOS process skew, leading to signal collisions and reduced throughput.
Innovation Solution
Implementing a trim circuit on each memory die within the stack to adjust and equalize signal delays, ensuring all dies operate with a consistent net timing delay, thereby minimizing signal collisions and maintaining high data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional memory is stacked to increase density, then memory density is improved, but signal alignment and timing issues worsen due to internal connection delays and CMOS process skew
Solution Approach 1:
The patent applies local quality by implementing individual trim circuits on each memory die to provide localized delay adjustment. Each die can independently tune its signal delay to compensate for variations in internal connection delays and CMOS process skew, ensuring that signals from different stacked dies arrive at the controller simultaneously despite physical and manufacturing variations.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the delay parameter of signals transmitted from each memory die through trim circuits. By dynamically modifying the delay parameter, the system compensates for timing variations caused by stacking, maintaining signal alignment without requiring changes to the physical stack configuration or memory cell architecture.
2Quantity of substance
If additional memory is stacked to increase density, then memory density is improved, but signal transmission delays increase
Solution Approach 1:
The patent addresses signal transmission delays by changing the delay parameter through trim circuits on each die. These circuits add or subtract time delays to signals before they are transmitted through the stack, effectively equalizing the total transmission time across all dies and compensating for the increased physical distance in stacked configurations.
Solution Approach 2:
The trim circuits perform preliminary action by pre-adjusting signal delays before transmission occurs. This proactive timing adjustment ensures that signals from dies at different positions in the stack are synchronized at the source, preventing timing conflicts and reducing the need for complex retry logic or error correction mechanisms.
3Reliability
If trim circuits are added to each memory die to adjust delays, then signal alignment is improved, but device complexity increases
Solution Approach 1:
The trim circuits are designed with universality to perform multiple functions: they adjust signal delays, compensate for process variations, and synchronize timing across different dies. This multi-functionality reduces the need for separate compensation circuits and simplifies the overall system architecture despite the added complexity of individual die adjustments.
Solution Approach 2:
The trim circuits implement self-service by automatically adjusting their own delay parameters based on feedback from signal timing measurements. Each die can independently calibrate its trim circuit to achieve optimal synchronization, reducing the need for complex external control logic and simplifying the overall timing management architecture.
Data Source
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AI summary
A device (10) includes a first memory die (60) and a second memory die (62) directly coupled to the first memory die (60) via a first bus (64). The device (10) also includes a second bus (48) directly coupled to the first memory die (60). The first memory die (60) includes a first trim circuit (88) that when in operation adjusts a delay of signal transmission by the first memory die (60) to a first value, while the second memory die (62) comprises a second trim circuit (88) that when in operation adjusts a delay of signal transmission by the second memory die (62) by a second value.