Stacked Memory Signal Delay Calibration for PVT Skew Correction
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Solution Overview
Problem
The existing stacked semiconductor memory apparatuses face issues with signal skew due to PVT variations, which reduce timing margins and data transmission efficiency, particularly in high-speed operations, as multiple slave chips share a single path for timing signals, leading to deterioration in operation characteristics.
Innovation Solution
Incorporating a variable delay unit that detects PVT variations in each slave chip and generates a delay timing signal to adjust the first timing signal AYP, ensuring the second timing signal PIN is activated at the target timing, thereby reducing skew and increasing timing margins through the use of reference and process delay values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple slave chips share a single path for timing signals and data transmission, then device complexity is reduced, but signal skew increases due to PVT variations
Solution Approach 1:
The patent measures process delay values during an initial calibration phase before normal operation begins. These measured values are stored and used to pre-compensate for PVT variations during subsequent signal transmission, preventing timing skew before it occurs rather than correcting it after the fact.
Solution Approach 2:
The patent dynamically adjusts delay compensation parameters based on the measured process delay values. By changing the delay parameters according to the specific characteristics of each slave chip, the system compensates for PVT variations and maintains accurate timing synchronization across all chips sharing the common path.
2Manufacturing precision
If the number of TSVs is reduced to improve layout and available area, then manufacturing precision is improved, but timing signal skew increases
Solution Approach 1:
The patent measures the actual process delay values that result from the reduced TSV configuration and uses these measurements to adjust delay compensation parameters. This allows the system to maintain accurate timing despite the physical constraints imposed by having fewer TSVs for signal transmission.
Solution Approach 2:
The patent creates a model of the timing characteristics by measuring process delay values from each slave chip during calibration. This copied information about the specific timing characteristics is then used to compensate for variations without needing additional physical transmission paths or TSVs.
3Productivity
If slave chips are fabricated from different wafers to increase production capacity, then productivity is improved, but process variation increases causing significant timing skew
Solution Approach 1:
The patent implements a feedback mechanism where process delay values are measured from each slave chip during calibration. These measured values provide feedback about the specific timing characteristics of chips from different wafers, allowing the system to compensate for inter-wafer process variations and maintain synchronization.
Solution Approach 2:
The patent adjusts delay compensation parameters based on the measured process delay values from each individual slave chip. This parameter adjustment compensates for the process variations inherent in fabricating chips from different wafers, allowing high production capacity while maintaining timing accuracy.
4Speed
If timing margins are reduced to increase data transmission speed, then speed is improved, but timing skew has a greater negative impact on effective data area
Solution Approach 1:
The patent performs preliminary measurement of process delay values during calibration before normal high-speed operation begins. By knowing the timing characteristics in advance, the system can operate at higher speeds with smaller timing margins while still maintaining reliable synchronization through pre-determined compensation values.
Solution Approach 2:
The patent dynamically adjusts delay compensation parameters to optimize timing margins for high-speed operation. By changing the compensation parameters based on measured process delay values, the system maintains adequate timing margins even when operating at higher data transmission speeds where margins are inherently smaller.
Data Source
AI summary
The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.