Stacked Semiconductor Memory Testing via Delay Control

The patent divides the testing function into separate segments by providing dedicated test control circuits within each data storage region. Each region can be tested independently through its own test control signal input, allowing parallel testing of multiple stacked dies without requiring additional external pins. This segmentation enables each die to perform different test operations simultaneously while maintaining individual test capability.

The patent transitions from a single-dimension testing approach (sequential testing through limited pins) to a multi-dimensional approach by enabling simultaneous testing across multiple stacked dies. Each die operates in its own test dimension with independent control signals, allowing the system to test multiple regions in parallel rather than sequentially, effectively adding a temporal dimension to the testing capability.

The patent implements universal test control circuits that can operate in multiple modes - both independent die testing and coordinated multi-die testing. The test control signals are designed to be universally applicable across all data storage regions, allowing the same basic control structure to manage both independently operating dies and stacked dies, thereby reducing overall test control complexity despite the independent operation of each die.

The patent introduces internal test control circuits as intermediary elements between the external test interface and the data storage regions. These intermediary circuits receive test control signals and distribute them appropriately to each die, managing the complexity of independent die operation while maintaining a simplified external interface. The intermediaries handle the coordination logic, allowing independent die operation without exposing the full complexity externally.

The patent applies local quality by allowing different test control signals to be applied to different data storage regions simultaneously. Each region can receive customized test signals tailored to its specific testing requirements, enabling precise diagnostic control for each die while maintaining simultaneous operation. This local customization of test signals ensures that each region undergoes the appropriate test for its function and condition.

The patent implements dynamic test control where the test signals applied to each data storage region can vary independently in timing, pattern, and sequence. The test control circuits dynamically adjust the test parameters for each die based on its specific testing needs, allowing simultaneous testing with differentiated control. This dynamic capability enables both high testing efficiency through parallel operation and high diagnostic precision through customized test patterns for each region.