Stacked Oxide-Semiconductor Memory Cells for Higher Density Retention
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high storage capacity per unit area and efficient data storage due to limitations in memory cell stacking and data retention.
Innovation Solution
A semiconductor device with a novel structure featuring stacked memory cells, including transistors and capacitors with oxide semiconductors, where the channel length direction of one transistor is perpendicular to the channel length direction of another, allowing for increased storage capacity and improved data retention through reduced off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity per unit area is improved, but device structure complexity increases
Solution Approach 1:
The patent implements three-dimensional stacking of memory cells in the vertical direction, transitioning from planar two-dimensional arrangement to three-dimensional configuration. Multiple memory cell layers are stacked above each other, with word lines and bit lines extending through multiple layers, thereby increasing storage capacity per unit area by utilizing the vertical dimension.
Solution Approach 2:
The patent employs a nested structure where multiple memory cell layers are stacked within a compact vertical space. Each memory cell layer contains transistors and capacitors that are integrated and nested together, with shared wiring structures that pass through multiple layers, creating a densely packed three-dimensional memory architecture.
2Reliability
If oxide semiconductors are used to reduce off-state current, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes oxide semiconductor materials with specific physical and electrical parameters, particularly their extremely low off-state current characteristics. By selecting and optimizing the oxide semiconductor material composition and structure, the patent achieves superior data retention while managing the precision requirements through material property optimization rather than purely geometric precision control.
Data Source
AI summary
The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.