Stacked Memory Die Bonding for Low-Height Semiconductor Packages

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Solution Overview

Problem

The existing semiconductor packages face limitations in reducing the height of stacked memory dies when bonding pads with bumps, which hinders the integration and storage capacity of the package.

Innovation Solution

A semiconductor package design where memory layers are formed by directly attaching pairs of memory dies without bumps, using Cu-Cu bonding, and stacking subsequent layers with bumps, allowing for increased integration and storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If memory dies are bonded using bumps, then electrical connectivity is achieved, but the height of stacked memory dies cannot be reduced sufficiently

Engineering Contradiction:
Improveheight of stacked memory diesVSAvoidelectrical connectivity
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The bonding process is segmented into two distinct stages: (1) bump-free bonding for initial memory die attachment to reduce height, and (2) subsequent bump formation for electrical connectivity. This segmentation allows each stage to optimize for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Memory dies are bonded together in advance without bumps to achieve minimal height, and electrical connectivity is established later through bump formation. This preliminary bonding action resolves the height constraint before electrical connection requirements are addressed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory dies are stacked with bumps for electrical connectivity, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidstacking structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stacking structure is divided into bump-free regions for mechanical support and bump regions for electrical connectivity. This segmentation simplifies the overall structure by assigning specific functions to specific regions, reducing the complexity of integrating both mechanical and electrical functions simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the memory die stack have different properties: some areas have bumps for electrical connection while other areas remain bump-free for height reduction. This local differentiation allows the structure to meet both reliability and simplicity requirements in their respective zones.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If more memory dies are stacked to increase storage capacity, then storage capacity improves, but the height of the package increases

Engineering Contradiction:
Improvestorage capacityVSAvoidpackage height
Core Design Contradiction:
Quantity of substanceVSLength of stationary object

Solution Approach 1:

The bonding approach is made dynamic by using bump-free bonding for initial stacking to minimize height, then adding bumps selectively for electrical connectivity. This dynamic approach allows the package to accommodate more memory dies within a constrained height by adapting the bonding method to each stacking stage.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The bonding parameters are changed between stacking stages: initially using bump-free bonding with specific pressure and temperature parameters to achieve close stacking, then changing to bump formation parameters for electrical connection. This parameter change enables increased die count without proportional height increase.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the integration and storage capacity of semiconductor packages by reducing the height of the memory dies while maintaining electrical connectivity, allowing for more memory dies to be packed in a smaller form factor.

Implementation Method 1

directly attaching pairs of memory dies without bumps, using Cu-Cu bonding

Methodology Applied
Scientific EffectCu-Cu bonding: Diffusion Welding

Data Source

PatentUS20240347524A1Semiconductor package
Publication Date: 2024.10.17 SAMSUNG ELECTRONICS CO LTD
  • US20240347524A1 patent drawing
  • US20240347524A1 patent drawing
  • US20240347524A1 patent drawing

AI summary

A semiconductor package according to an example embodiment of the present disclosure includes: a package substrate; and first to third memory dies disposed on the package substrate and sequentially stacked in a first direction, perpendicular to an upper surface of the package substrate, and the first memory die and the second memory die are attached to each other without a bump, and the second memory die and the third memory die are attached to each other by a plurality of bumps.