Stacked Memory Die Evaluation Using Known Good Die Bonding
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Solution Overview
Problem
Existing wafer-to-wafer bonding techniques in semiconductor manufacturing result in low device yield due to bonding good dies with defective dies, leading to waste and increased production costs, without intermediate evaluation procedures to identify operable dies before completion.
Innovation Solution
Implementing reconstructed semiconductor die evaluation by separating and testing dies to identify Known Good Dies (KGDs), forming semiconductor devices with intermediate evaluation procedures, and using conductive pads for evaluation interfaces to reduce defective bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-to-wafer bonding is performed without intermediate evaluation, then manufacturing process is simplified and faster, but device yield decreases due to bonding good dies with defective dies
Solution Approach 1:
The patent performs die evaluation and identification of Known Good Dies (KGDs) before the wafer-to-wafer bonding process. This preliminary action allows defective dies to be identified and excluded from bonding, ensuring that only good dies are bonded together. The evaluation includes functional testing and characterization of dies at an intermediate stage, enabling selective bonding based on die quality without compromising manufacturing efficiency.
2Reliability
If intermediate evaluation procedures are implemented to identify operable dies, then device yield improves, but manufacturing process complexity and time increase
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: die preparation, intermediate evaluation, KGD identification, and selective bonding. This segmentation allows the evaluation process to be performed on specific die groups rather than entire wafers, reducing overall process complexity. The intermediate evaluation stage includes separate functional testing and characterization steps that can be independently optimized and controlled.
Solution Approach 2:
The patent introduces an intermediate evaluation stage as a mediator between die preparation and final bonding. This intermediary process includes evaluation circuitry and testing mechanisms that assess die functionality without requiring complete device assembly. The intermediate stage provides a controlled environment for die characterization, enabling informed decisions about which dies to bond while simplifying the overall manufacturing workflow.
3Loss of time
If all dies are bonded without selection, then manufacturing time is reduced, but electronic waste increases due to rejected defective dies
Solution Approach 1:
The patent performs preliminary die evaluation and KGD identification before bonding, allowing defective dies to be excluded from the bonding process entirely. This preliminary selection prevents good dies from being bonded with defective dies, eliminating the need to discard bonded assemblies later. The intermediate evaluation ensures that only known good dies are processed further, reducing electronic waste without significantly increasing manufacturing time.
Data Source
AI summary
Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.