Stacked Memory Die Segmentation for Signal Integrity
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Solution Overview
Problem
Current storage devices using flash memory face limitations in performance enhancement, particularly in speed and power consumption, and existing stacking configurations lead to inefficiencies in memory capacity and signal transmission quality.
Innovation Solution
A storage device configuration involving a stacked structure of two dies, where the first die includes multiple memory cell array circuits and the second die contains write/read and interface circuits, allowing for efficient data processing and communication, and the use of a CMOS-bonded-to-array (CBA) type device manufacturing process to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple storage devices are stacked to increase memory capacity, then memory capacity is improved, but signal transmission quality deteriorates and device complexity increases
Solution Approach 1:
The storage device is segmented into two separate dies: a first die containing multiple memory cell array circuits and a second die containing write/read circuit units. This segmentation allows each die to be optimized for its specific function, with the first die focusing on high-density storage and the second die on high-quality signal processing, thereby maintaining signal transmission quality while achieving high memory capacity through stacking.
Solution Approach 2:
The patent transitions from a single-die planar structure to a three-dimensional stacked structure with functional separation. By stacking the first die (memory arrays) and second die (write/read circuits) vertically, the patent achieves high memory capacity in the vertical dimension while keeping each die's signal transmission paths short and optimized, preventing signal waveform deterioration.
2Quantity of substance
If multiple stacked devices are used to achieve high memory capacity, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple memory cell array circuits into a single first die and combines write/read circuit units with interface circuits on a single second die. This consolidation reduces the number of separate devices needed, simplifying the overall system while achieving high memory capacity through the stacked configuration of these integrated dies.
3Ease of manufacture
If conventional storage device configuration is used, then manufacturing is simpler, but performance such as speed and power consumption cannot be improved
Solution Approach 1:
The patent changes the architectural parameters of the storage device by separating memory arrays and write/read circuits onto different dies, enabling independent optimization of each component. This allows the memory cell arrays to be designed for high density while the write/read circuits are optimized for high speed and low power consumption, achieving superior performance without significantly complicating the manufacturing process through standard CMOS bonding techniques.
Data Source
AI summary
A storage device includes a first die and a second die. The first die is stacked on the second die. The first die includes a plurality of die regions partitioned by dicing regions. Each of the die regions includes a memory cell array. The second die includes a circuit configured to process reading of data from and writing of data to, memory cells in the memory cell arrays in each of the die regions of the first die.