Stacked Memory Dies External Interface Architecture
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Solution Overview
Problem
Existing memory systems with stacked memory dies face challenges in efficient internal and external data transfers due to complex signaling requirements and the need for significant internal control signals, which can lead to increased complexity and cost.
Innovation Solution
The proposed solution involves a memory system architecture where some memory dies are connected externally to the stack and others internally, using a cascading connection for command, address, power, and ground signals, with a Compute Express Link (CXL) compliant host interface managed via PCIe, allowing for efficient data transfer and reduced internal control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex internal control signals are used for data transfer between stacked memory dies, then data transfer capability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple control signal functions into a unified signaling protocol that operates across the stacked memory dies. By merging command, address, and control functions into a standardized interface protocol, the system achieves efficient data transfer without requiring separate complex internal control signal paths between each die pair.
Solution Approach 2:
The patent implements a universal interface protocol that handles multiple functions (command issuance, address transmission, data transfer, control) through a single standardized signaling mechanism. This multi-functional approach eliminates the need for dedicated control signals for each operation type, reducing overall system complexity while maintaining full data transfer capability.
2Productivity
If multiple bank groups are implemented for parallel data transfer, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory address space and data paths into independent banks that can operate in parallel. Each bank group handles specific address ranges and data transfers independently, allowing simultaneous operations across multiple banks without requiring complex cross-bank control signaling. This segmentation enables parallelism while keeping individual bank control simple.
Solution Approach 2:
The patent introduces parallelism by adding a temporal dimension to data transfer operations, allowing multiple banks to operate simultaneously at different time slices or in concurrent pipelines. This dimensional approach to parallelism achieves high productivity without requiring complex spatial reorganization of bank groups, as each bank maintains its own simple control path.
3Ease of operation
If direct control signals are routed to each memory die, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary controller layer that manages signal distribution to multiple memory dies. This intermediary receives commands from the host, translates them into die-specific control signals, and routes them appropriately. This mediation simplifies the overall signal routing architecture by centralizing control logic, eliminating the need for complex direct point-to-point control signal paths between the host and each individual die.
Data Source
AI summary
Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.