Vertically Stacked Memory Arrays With Mixed Dopant Layers
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in the fabrication of tri-gate transistors on bulk silicon substrates, is a significant issue in integrated circuit manufacturing.
Innovation Solution
The integration of vertically stacked memory arrays with heterogeneous active layers, comprising first and second memory arrays of different dopant types, such as 4T SRAM and DRAM cells, facilitates efficient fabrication of tightly integrated memory resources, utilizing non-silicon semiconductor material layers for enhanced mobility and mobility control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked transistor structures. This dimensional change enables continued scaling and density improvement while maintaining effective channel control through the vertical architecture, where the gate wraps around the channel in multiple dimensions, providing superior electrostatic control compared to conventional planar devices.
Solution Approach 2:
The patent employs composite material structures including nanowire channels with specific crystal orientations, multiple semiconductor layers with different properties, and integrated dielectric and conductive materials. These composite structures enable simultaneous optimization of carrier mobility, short channel control, and thermal management in scaled devices.
2Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon, then manufacturing cost is reduced, but mobility improvement and short channel control deteriorate
Solution Approach 1:
The patent modifies fabrication parameters including crystal orientation selection, doping profiles, and thermal processing conditions to achieve enhanced mobility in vertically stacked structures. By changing these parameters, the patent maintains compatibility with bulk silicon processing while achieving superior device performance compared to conventional approaches.
Solution Approach 2:
The patent segments the transistor structure into multiple vertically stacked active regions, each with optimized characteristics. This segmentation allows independent optimization of different device regions for specific functions while maintaining overall cost-effectiveness through standardized fabrication processes for each segment.
Data Source
AI summary
Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are stacked with each other to form structures of respective memory arrays. In an embodiment, an IC die structure comprises first metal oxide semiconductor field effect transistors (MOSFETs) of a first active layer, and second MOSFETs of a second active layer which is vertically stacked with the first active layer. A first memory array comprises the first MOSFETs, and a second memory array comprises the second MOSFETs. The first memory array comprises a four transistor (4T) static random access memory (SRAM) cell, each transistor of which corresponds to a first dopant type. The second memory array comprises a second memory cell, each transistor of which corresponds to a second dopant type. In another embodiment, a cell density of the first memory array is substantially less than that of the second memory array.