Stacked Memory Chip Dummy-Region Resistors for Smaller Layouts
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Solution Overview
Problem
The increasing demand for high-density integration of semiconductor memory devices poses challenges in achieving a compact design while maintaining effective operation.
Innovation Solution
A semiconductor memory device is designed with a CoP structure, where a first chip includes a cell region with memory cells and a dummy region with dummy cell transistors, and a second chip includes core circuits and peripheral circuits. The dummy region incorporates variable resistors formed by serially connecting dummy cell transistors, allowing for independent control of resistance values based on gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If active resistors are used in the dummy region, then the circuit operation is simple, but the chip area is large
Solution Approach 1:
The patent changes the operational parameters of the dummy cell transistors by controlling their gate voltages to operate in the linear region, transforming them into variable resistors. This parameter change allows the transistors to replace active resistors, significantly reducing chip area while providing adjustable resistance values through voltage control
Solution Approach 2:
The patent introduces dynamic control of resistance values through variable gate voltages applied to the dummy cell transistors. This dynamic capability allows the resistance to be adjusted during operation, providing flexibility that static active resistors cannot offer, while maintaining the space-efficient transistor-based implementation
2Adaptability or versatility
If more dummy cell transistors are added to form variable resistors, then the resistance control flexibility increases, but the manufacturing complexity increases
Solution Approach 1:
The patent makes the dummy cell transistors multi-functional by having them serve both as test structures for characterizing transistor performance and as functional variable resistors for voltage division and reference voltage generation. This universal usage eliminates the need for separate resistor structures, simplifying manufacturing while providing versatile resistance control
Solution Approach 2:
The patent divides the dummy region into multiple segments of dummy cell transistors that can be independently controlled through separate gate voltage lines. This segmentation allows flexible combination of transistor segments to achieve desired resistance values, providing adaptability without requiring entirely separate circuit structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a chip-size gain by replacing active resistors with variable resistors in the dummy region, optimizing space utilization and enhancing operational efficiency.
Implementation Method 1
The dummy region of the first chip may include at least one variable resistor that includes the set of dummy cell transistors... A respective resistance value of each of the plurality of variable resistors may be controlled independently based on a voltage applied to a gate line of the ones of the dummy cell transistors included in a corresponding one of the plurality of variable resistors
Data Source
AI summary
A semiconductor memory device includes a first chip including a cell region including memory cells and a dummy region that includes dummy cell transistors, and a second chip including core circuits and peripheral circuits configured to control operation of the memory cells, the first chip and the second chip overlap along a vertical direction. The dummy region of the first chip may include at least one variable resistor that includes the dummy cell transistors.