3D Stacked Nonvolatile Memory Using Upper-Stack Dummy Word-Lines
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Solution Overview
Problem
Nonvolatile memory devices with three-dimensional structures face increased program disturbance due to the reduction in critical dimension of channel holes, leading to performance degradation and disturbance in unselected memory cells during programming.
Innovation Solution
The nonvolatile memory device is designed with a control circuit that applies a program voltage to a selected word-line and reduces the voltage level of dummy word-lines in upper stacks or sub-blocks during the program execution period, effectively turning off dummy memory cells and blocking program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension of channel holes is reduced to increase integration degree and memory capacity, then memory capacity increases, but program disturbance on unselected memory cells increases
Solution Approach 1:
The memory block is divided into multiple stacks, with each stack containing a portion of the cell strings. Dummy word-lines are selectively applied to specific stacks (e.g., upper stacks) during programming operations on other stacks, allowing localized suppression of program disturbance without affecting the entire memory array. This segmentation enables targeted interference management while maintaining high integration density.
Solution Approach 2:
Different voltage conditions are applied to different regions of the memory array based on their operational state. During programming of a selected stack, dummy word-lines are activated only in unselected stacks that are adjacent or proximal to the selected stack, creating localized voltage conditions that prevent program disturbance in those specific regions while maintaining normal operation in the selected region.
2Object-affected harmful factors
If dummy word-lines are applied to all stacks during programming, then program disturbance is reduced, but voltage control complexity and energy consumption increase
Solution Approach 1:
The memory block is divided into multiple stacks, with each stack containing a portion of the cell strings. Dummy word-lines are selectively applied to specific stacks (e.g., upper stacks) during programming operations on other stacks, allowing localized suppression of program disturbance without affecting the entire memory array. This segmentation enables targeted interference management while maintaining high integration density.
Solution Approach 2:
Instead of applying dummy word-lines to all stacks uniformly, the invention applies dummy voltages only to specific stacks (such as upper stacks) that are most susceptible to program disturbance from the selected stack. This partial application reduces the overall complexity and energy consumption compared to a universal approach, while still achieving sufficient protection against program disturbance.
3Productivity
If high voltage is applied to selected word-line for programming, then programming speed improves, but soft erase and hot carrier injection occur in unselected memory cells
Solution Approach 1:
Before applying the high program voltage to the selected word-line, dummy voltages are pre-applied to the dummy word-lines in unselected stacks. This preliminary action creates a protective voltage condition that counteracts the potential harmful effects (soft erase and hot carrier injection) that would otherwise occur when the high program voltage is applied, thereby preventing data integrity issues before they can happen.
Solution Approach 2:
Dummy word-lines serve as intermediary elements between the selected word-line and the unselected memory cells. When high voltage is applied to the selected word-line for programming, the dummy word-lines in unselected stacks act as mediators by maintaining specific voltage levels that prevent the high voltage from causing harmful effects in the unselected memory cells, thus protecting data integrity while allowing fast programming.
Data Source
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AI summary
A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.