Stacked Memory ECC Layout for Faster Error Correction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in integrating error correction circuits efficiently, leading to increased area requirements and decreased operating speed due to the need for additional error correction components and operations.
Innovation Solution
A semiconductor memory device with a CoP structure, where the memory cell array and error correction circuit are vertically overlapped in separate semiconductor structures, allowing for improved integration and reduced physical distance between them, enhancing signal transfer and operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits are integrated in the same semiconductor structure as memory cells, then error correction function is provided, but area requirement increases and operating speed decreases
Solution Approach 1:
The patent divides the semiconductor device into two separate structures: a first semiconductor structure containing memory cell arrays, and a second semiconductor structure containing error correction circuits. This segmentation allows each structure to be optimized independently, reducing the area required on the main chip while maintaining full error correction functionality.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture by bonding the second semiconductor structure onto the first semiconductor structure. This vertical stacking enables error correction circuits to occupy a different spatial dimension, effectively reducing the two-dimensional chip area requirement while maintaining functional integration.
2Reliability
If error correction circuits are integrated in the same semiconductor structure as memory cells, then error correction function is provided, but operating speed decreases
Solution Approach 1:
By separating error correction circuits into a distinct second semiconductor structure, the patent enables independent optimization of signal paths. The segmented architecture allows for dedicated, optimized connection routes between memory cells and error correction circuits, reducing signal interference and improving operating speed.
Solution Approach 2:
The patent introduces bonding pads as intermediary connection points between the first and second semiconductor structures. These bonding pads provide optimized electrical interfaces that facilitate high-speed signal transfer between memory cell arrays and error correction circuits, mitigating the speed penalty typically associated with integrated error correction.
3Area of stationary object
If memory cell arrays and error correction circuits are vertically overlapped in separate semiconductor structures, then space utilization improves and operating speed enhances, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into two separately manufacturable semiconductor structures that can be produced using standard fabrication processes. This segmentation allows each structure to be manufactured and tested independently before bonding, reducing overall manufacturing complexity despite the advanced stacked architecture.
Solution Approach 2:
The patent implements a nested structure where the second semiconductor structure (containing error correction circuits) is bonded onto and overlaps with the first semiconductor structure (containing memory cells). This nested arrangement maximizes space utilization while maintaining separate manufacturing pathways for each layer, simplifying the overall fabrication process.
Data Source
AI summary
A semiconductor memory device includes a memory cell array in a first semiconductor structure and including a memory area configured to store main data and a parity area configured to store parity data corresponding to the main data, a first ECC engine in a second semiconductor structure bonded to the first semiconductor structure through metal pads, configured to generate parity data corresponding to write main data, and to generate check data corresponding to read main data, a second ECC engine in the second semiconductor structure and configured to generate an error correction signal based on the parity and check data, and a data corrector in the second semiconductor structure and configured to correct read main data from the memory area based on the error correction signal. The first ECC engine and the data corrector vertically overlap the memory area, and the second ECC engine vertically overlaps the parity area.