Stacked Memory Spare Resource Repair via ECC

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Solution Overview

Problem

Current 3D memory repair methods require high spare resource utilization, leading to discarding entire memory stacks when available spare resources are insufficient, especially during the post-bond process, resulting in low yield and inefficiency.

Innovation Solution

Implementing an error correction module in the system layer that stores and manages spare resource information, allowing for error detection and correction using spare memory, and variably utilizing spare resources across both pre-bond and post-bond processes to ensure additional spare resources are available for repair.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If spare resources are used for repair in the pre-bond process only, then the repair process is simple, but the available spare resources are insufficient for post-bond repair

Engineering Contradiction:
Improverepair process complexityVSAvoidavailable spare resources
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent performs preliminary error detection and spare resource allocation in the pre-bond process, storing failure information in defective memory before bonding. This preliminary action allows the system to prepare repair strategies in advance, enabling more effective utilization of spare resources during post-bond repair without increasing overall process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces defective memory as an intermediary component that stores failure information and coordinates between pre-bond and post-bond repair processes. This intermediary enables information exchange and coordination, allowing spare resources to be effectively utilized across both repair stages without requiring complex direct integration between processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If entire memory stack is discarded when spare resources are insufficient, then repair reliability is maintained, but manufacturing yield decreases

Engineering Contradiction:
Improverepair reliabilityVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic spare resource allocation where the system adaptively determines repair strategies based on actual failure patterns stored in defective memory. Instead of static pre-bond-only or post-bond-only repair approaches, the system dynamically selects and combines repair methods (ECC correction, spare cell substitution) based on real-time error detection results, maintaining reliability while maximizing yield.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of spare resources between pre-bond and post-bond processes. Spare cells are configured for specific repair tasks in pre-bond, then reconfigured or supplemented in post-bond based on actual failure modes. This parameter flexibility allows the same spare resources to serve multiple repair scenarios, improving yield without compromising reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If ECC is used to correct errors, then repair capability is improved, but additional check bits and processing complexity are required

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies ECC error correction selectively rather than universally. The system detects errors and applies ECC correction only to specific data bits that require correction, rather than processing all data uniformly. This partial action approach provides effective error correction capability while minimizing the additional processing complexity and overhead associated with full ECC implementation.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11315657B2Stacked memory apparatus using error correction code and repairing method thereof
Publication Date: 2022.04.26 IND ACADEMIC COOP FOUND YONSEI UNIV
  • US11315657B2 patent drawing
  • US11315657B2 patent drawing
  • US11315657B2 patent drawing

AI summary

The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.