Stacked Memory ECC Routing for Physically Grouped Bit Errors
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Solution Overview
Problem
Existing memory systems with stacked architectures face limitations in error correction capabilities, particularly when bit errors occur across multiple blocks, as current error correction codes are unable to correct errors beyond a certain block size, leading to uncorrectable errors.
Innovation Solution
Implementing data routing techniques that allocate error correction engines to subsets of data based on physical arrangements of memory arrays, allowing for more effective correction of bit errors by distributing error correction operations across multiple engines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If error correction codes are applied to larger block sizes to cover more memory, then the coverage area increases, but the ability to correct errors deteriorates because current ECC cannot correct errors beyond certain block sizes
Solution Approach 1:
The patent divides the memory system into multiple independent error correction domains, each with its own ECC engine. Instead of using a single ECC engine for the entire memory, the system creates multiple smaller ECC domains that can independently correct errors. This segmentation allows each ECC engine to operate within its corrected block size limits while collectively covering the entire memory space, thus resolving the contradiction between coverage area and error correction capability.
2Reliability
If data is routed through multiple error correction engines to improve error correction, then the error correction capability improves, but the system complexity increases
Solution Approach 1:
The patent introduces a routing mechanism that acts as an intermediary between the memory array and multiple ECC engines. This routing logic directs data to appropriate ECC engines based on the physical arrangement of memory blocks, enabling effective error correction without requiring complex integration. The routing layer simplifies the overall system architecture by providing a clear data flow path while maintaining the benefits of multiple ECC engines.
3Reliability
If multiple error correction engines are used to handle different data subsets, then the error correction effectiveness improves, but the manufacturing complexity increases
Solution Approach 1:
The patent assigns specific memory block subsets to specific ECC engines based on their physical arrangement in the stacked memory architecture. Each ECC engine is optimized to handle particular data subsets from specific memory blocks, creating local specialization. This approach improves error correction effectiveness for physically correlated errors while maintaining manufacturing simplicity by leveraging the existing physical layout rather than requiring complex reconfiguration during manufacturing.
Data Source
AI summary
Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.