3D Stacked Semiconductor Memory Structure With Shorter Electrical Paths
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues with dimension reduction and power consumption.
Innovation Solution
The semiconductor device design incorporates a bottom die with stacked structures, including a first controller die and storage dies configured as a floating array, and a second controller die with storage dies featuring an insulator-conductor-insulator structure, integrated through interconnect units, which reduces dimensions and electrical paths, thereby enhancing performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor device dimensions are scaled down to improve computing ability, then device size is reduced, but quality, yield, performance, and reliability deteriorate while complexity increases
Solution Approach 1:
The patent transitions from planar 2D device layout to three-dimensional stacked structures, stacking multiple dies vertically to achieve higher integration density without further reducing individual die dimensions. This dimensional change allows continued scaling benefits while maintaining device performance and reliability through better electrical path management and reduced interference.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate dies that are stacked and bonded together, with each die performing specific functions. This segmentation allows independent optimization of each die while reducing overall complexity and improving yield through modular manufacturing approaches.
2Ease of manufacture
If conventional planar structures are used, then manufacturing is simpler, but device dimensions and power consumption are higher
Solution Approach 1:
The patent employs vertical stacking of multiple dies in the third dimension, achieving compact device dimensions without complicating the manufacturing process of individual dies. Each die can be manufactured using conventional planar processes, then bonded together through standardized interconnect structures.
Solution Approach 2:
The patent implements a nested structure where multiple functional dies are stacked within a compact vertical space, with each die containing its own circuitry and being interconnected through through-substrate vias, creating a space-efficient three-dimensional integration.
3Reliability
If longer electrical paths are used in conventional structures, then device functionality is achieved, but power consumption increases
Solution Approach 1:
The patent uses vertical through-substrate vias to create direct electrical pathways between stacked dies, significantly shortening the electrical paths compared to lateral connections in planar structures. This three-dimensional interconnection reduces resistance and capacitance, thereby lowering power consumption while maintaining full device functionality.
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device including providing a first stacking structure comprising a first controller die, and a plurality of first storage dies sequentially stacked on the first controller die; providing a second stacking structure comprising a second controller die, and a plurality of second storage dies sequentially stacked on the second controller die; bonding the first controller die onto a bottom die through a plurality of first interconnect units; and bonding the second controller die onto the bottom die through a plurality of second interconnect units. The plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array. The plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.