Stacked Memory Cell Architecture With Integrated Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices require additional memory regions and controllers for error detection and correction, which increases complexity and area usage.
Innovation Solution
A memory device with a stacked structure, including a first-element layer with memory cells, a second-element layer with an error detection circuit, and a semiconductor substrate with a driver circuit, where transistors in both the memory cells and error detection circuits use metal oxides and have front and back gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ECC memory structure is used to provide error detection function, then data reliability is improved, but device complexity and chip area increase
Solution Approach 1:
The patent combines the error detection circuit with the memory cell array by using the same metal oxide semiconductor transistors and integrating both functions within the same stacked structure. The error detection circuit shares the same semiconductor layer technology and manufacturing process as the memory cells, merging what would traditionally be separate functional blocks into a unified device architecture.
Solution Approach 2:
The metal oxide semiconductor transistors serve dual purposes: they function as switching elements in the memory cells for data storage and as switching elements in the error detection circuit for data validation. This multi-functionality eliminates the need for separate transistor sets for each function, reducing overall device complexity.
2Reliability
If an ECC memory structure is used to provide error detection function, then data reliability is improved, but chip area increases
Solution Approach 1:
The patent employs a stacked three-dimensional structure where memory cells and error detection circuits are arranged in vertical layers rather than occupying separate horizontal areas. This vertical integration allows both functions to coexist on the same chip footprint, significantly reducing the required chip area compared to traditional planar ECC memory designs.
Solution Approach 2:
The error detection circuit is nested within the same stacked structure as the memory cells, with both functions integrated into the same vertical columnar architecture. The error detection transistors are positioned in the same element layer as memory cells, effectively nesting the error detection functionality within the memory structure itself.
3Use of energy by moving object
If metal oxide semiconductor transistors are used in memory cells, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the unique electrical characteristics of metal oxide semiconductor transistors, particularly their extremely low off-state current properties, to achieve low power consumption in the memory cells. By leveraging these inherent material properties rather than relying on complex circuit designs, the patent reduces power consumption while maintaining manufacturability through standard thin-film fabrication processes.
Data Source
AI summary
A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.