3D Stacked Memory Repartitioning for Isolating Error Regions
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Solution Overview
Problem
Current semiconductor memory subsystems face a mismatch in performance with modern host processors, leading to inefficiencies such as high idle times due to memory request delays, and struggle to balance bandwidth and density, with limitations in JEDEC interface standards and lack of memory power optimization.
Innovation Solution
The implementation of a stacked-die 3D memory architecture with shared control logic and memory vaults, enabling concurrent data transfer and reconfigurable interfaces to enhance energy efficiency and scalability, and the use of memory vault controllers and fabric control registers to manage communication links and error tracking for adaptive operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher bandwidth memory subsystems are implemented, then data transfer speed is improved, but the number of memory cards that can be connected is limited due to JEDEC electrical specifications
Solution Approach 1:
The memory subsystem is segmented into multiple independent memory vaults, each capable of operating at different bandwidths. This allows the system to connect multiple memory cards by dividing them into separate vaults, thereby resolving the limitation on the number of connectable memory cards while maintaining high data transfer speeds within each vault.
Solution Approach 2:
The memory subsystem implements dynamic configuration where memory vaults can be independently enabled or disabled based on system needs. This dynamic adaptability allows the system to optimize the number of active memory cards connected, overcoming the static limitations imposed by JEDEC electrical specifications.
2Speed
If memory bandwidth is increased, then performance is improved, but memory power optimization is compromised
Solution Approach 1:
The memory subsystem is divided into multiple independent memory vaults that can be independently powered and configured. This segmentation enables selective activation of only the necessary memory vaults, optimizing power consumption while maintaining required bandwidth performance by keeping unused vaults in a low-power state.
Solution Approach 2:
The system dynamically changes operational parameters such as bandwidth configuration and power state for each memory vault based on actual system needs. This allows the memory subsystem to operate at high bandwidth when needed while consuming minimal power during normal operation, resolving the contradiction between performance and power optimization.
3Speed
If the interface between host processor and memory subsystem is customized, then performance is optimized, but redesign is required when processor or memory technologies change
Solution Approach 1:
The memory vault interface is designed with universal, standardized connections that can accommodate different processor and memory technologies. This multi-functional interface design allows the same physical interface to support various technology generations without requiring redesign, while still achieving optimized performance through configurable vault configurations.
4Reliability
If error correction codes are applied to all memory portions, then reliability is improved, but write buffer requirements and complexity increase
Solution Approach 1:
ECC protection is applied selectively to specific memory portions (vaults) based on their error characteristics rather than uniformly across all memory. This local quality approach improves reliability for error-prone regions while minimizing the complexity and write buffer requirements by avoiding unnecessary ECC overhead in already-reliable memory portions.
Data Source
AI summary
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.