Stacked Memory Structure With Etch Stop for Contamination Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving compactness, multifunctionality, and high performance while maintaining reliability, particularly in the integration of peripheral circuit structures with memory cell arrays.
Innovation Solution
A semiconductor memory device is designed with a stacked structure that includes a peripheral circuit structure on a memory cell array, featuring a peripheral epi layer with an etch stopping layer and a contaminant penetration prevention layer to enhance thickness uniformity and reduce contamination during manufacturing, thereby improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a peripheral circuit structure is stacked on a memory cell array structure to achieve compactness and multifunctionality, then device integration and functionality are improved, but manufacturing precision and reliability deteriorate due to contamination and thickness non-uniformity
Solution Approach 1:
An etch stopping layer is introduced as an intermediary between the memory cell array structure and the peripheral circuit structure. This layer serves as a mediator that prevents contamination from propagating upward while maintaining thickness uniformity during the stacking manufacturing process, thus resolving the contradiction between achieving multifunctionality and maintaining manufacturing precision.
Solution Approach 2:
The stacked structure is segmented into distinct functional layers with the etch stopping layer and contaminant penetration prevention layer separating the memory cell array from the peripheral circuit. This segmentation allows independent optimization of each layer's manufacturing parameters, enabling both multifunctionality and manufacturing precision to be achieved simultaneously.
2Volume of moving object
If a peripheral circuit structure is stacked on a memory cell array structure to achieve compactness, then device size is reduced, but reliability deteriorates due to contamination during manufacturing
Solution Approach 1:
The etch stopping layer acts as a protective intermediary that blocks contamination pathways in the stacked structure. By introducing this intermediate layer, the patent enables compact device design while maintaining reliability through contamination prevention during manufacturing processes.
Solution Approach 2:
The contaminant penetration prevention layer is positioned beforehand in the stacked structure to cushion against potential contamination during subsequent manufacturing steps. This preemptive measure ensures that the compact stacked structure maintains high reliability despite the increased manufacturing complexity.
3Volume of moving object
If conventional stacking methods are used to integrate peripheral circuits on memory cell arrays, then device compactness is achieved, but manufacturing complexity increases due to contamination control requirements
Solution Approach 1:
The manufacturing process is segmented into distinct stages with the etch stopping layer serving as a clear boundary. This segmentation simplifies the overall manufacturing complexity by allowing separate process optimization for the memory cell array fabrication and the peripheral circuit fabrication, while still achieving compact device size through stacking.
Solution Approach 2:
The etch stopping layer serves as an intermediary that simplifies manufacturing by providing a clear process boundary and contamination barrier. This intermediate layer reduces the overall manufacturing complexity of the stacked structure by preventing contamination propagation between manufacturing stages.
Data Source
AI summary
A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.