Vertically Stacked Memory-Cell Strings With Etch-Stop Layers
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Solution Overview
Problem
Existing methods for forming memory arrays with vertically-stacked memory cells face challenges in efficiently forming and connecting wordlines in a stair-step structure, which affects the reliability and efficiency of data storage.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is used to form a memory array with vertically-stacked memory cells, utilizing alternating tiers of conductive and insulative materials, and etching techniques to create channel openings and trenches, followed by deposition of transistor and memory cell materials to form conductive lines and strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form memory arrays with vertically-stacked memory cells, then the basic structure can be formed, but the efficiency and reliability of data storage is compromised due to challenges in forming and connecting wordlines in a stair-step structure
Solution Approach 1:
The patent applies preliminary action by forming the stair-step structure and channel openings before forming the memory cell materials. The sacrificial material is placed in channel openings that extend through alternating tiers, and the memory cell materials are formed to conformally coat the channel openings and fill the sacrificial material spaces. This preliminary structuring enables reliable wordline formation and connection without compromising data storage reliability.
Solution Approach 2:
The patent segments the memory array structure into alternating tiers of conductive and insulative materials, with channel openings extending through specific tiers. The stair-step structure is divided into discrete steps corresponding to individual wordlines, each formed in a controlled manner. This segmentation allows for precise formation and connection of wordlines, improving reliability while managing the inherent complexity of the three-dimensional architecture.
2Productivity
If gate-last or replacement-gate processing is used to form memory arrays, then connectivity and data storage capabilities are improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate-last or replacement-gate processing method is applied by first forming the channel openings and sacrificial material structure, then forming the memory cell materials that will become the gates. This preliminary formation of the channel structure before gate formation enables better connectivity and data storage efficiency, as the gates are precisely positioned after the channel architecture is established.
Solution Approach 2:
The patent uses sacrificial material as an intermediary element during manufacturing. The sacrificial material is formed in channel openings, then memory cell materials are deposited conformally around it. After deposition, the sacrificial material is removed, leaving precisely formed channel structures and gates. This intermediary approach simplifies the overall manufacturing process by enabling sequential formation of complex structures without requiring simultaneous precise alignment.
3Stability of the object's composition
If non-stoichiometric silicon dioxide is used as an etch stop, then the stability and performance of the memory array are enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies non-stoichiometric silicon dioxide with a silicon-to-oxygen atomic ratio greater than 0.5 as the etch stop layer. This parameter change from stoichiometric to non-stoichiometric composition provides enhanced stability and performance of the memory array. The non-stoichiometric composition creates a more stable material structure that improves device performance while the specific atomic ratio control enables reliable etching processes.
Solution Approach 2:
The patent applies local quality by placing non-stoichiometric silicon dioxide specifically as an etch stop layer in alternating tiers of the memory array structure. This localized application of a material with specific compositional properties (silicon-to-oxygen ratio > 0.5) provides the necessary etching selectivity and structural stability at critical interfaces, enhancing overall array stability while managing manufacturing precision through targeted material placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and efficient formation of memory arrays with vertically-stacked memory cells, improving data storage capabilities and connectivity through the use of non-stoichiometric silicon dioxide as an etch stop, enhancing the stability and performance of the memory array.
Implementation Method 1
An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.