Stacked Memory Device Fail Address Storage via Column Decoders
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Solution Overview
Problem
Existing stacked memory devices lack efficient methods to increase storage space for fail addresses, limiting their usability in test modes.
Innovation Solution
A stacked memory device with a buffer die and multiple memory dies connected via through silicon vias (TSVs), where a test circuit in the buffer die detects defective cells in a target memory die and stores fail address information in column decoders of other memory dies, allowing for increased storage space and usability during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fail addresses are stored only in the target memory die during testing, then the storage space is limited, but the device structure remains simple
Solution Approach 1:
The patent merges the fail address storage function across multiple memory dies by utilizing column decoders in non-target memory dies as shared storage resources. This allows the stacked memory device to collectively store fail addresses from any target memory die, effectively increasing storage capacity without adding dedicated storage components.
Solution Approach 2:
The column decoders in non-target memory dies serve dual purposes: their original function of decoding column addresses and an additional function of storing fail address information. This multi-functionality approach increases storage space for fail addresses while avoiding the need for separate storage structures.
2Quantity of substance
If fail address information is stored in column decoders of other memory dies, then storage space increases, but data transmission complexity increases
Solution Approach 1:
The patent introduces the data input/output path as an intermediary channel that already exists in the stacked memory device structure. By utilizing this existing data transmission path for moving fail address information between memory dies, the system avoids creating new complex transmission channels while still enabling data movement across dies.
Solution Approach 2:
The data input/output path serves multiple functions including normal data read/write operations and the additional function of transmitting fail address information during testing. This multi-functional use of existing pathways increases storage capability without proportionally increasing transmission complexity.
3Adaptability or versatility
If more storage space is allocated for fail addresses, then usability in test mode improves, but manufacturing complexity increases
Solution Approach 1:
The patent makes existing column decoder structures multi-functional by enabling them to store fail address information in addition to their primary decoding function. This approach improves test mode usability without requiring new manufacturing processes or additional dedicated storage components, thereby avoiding increased manufacturing complexity.
Solution Approach 2:
The stacked memory device utilizes its own existing structural components (column decoders and data I/O paths) to provide the storage and transmission functions for fail addresses. This self-service approach allows the device to enhance its test capabilities using resources already present in its architecture, avoiding external additions that would complicate manufacturing.
Data Source
AI summary
A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die.