Vertically Stacked Memory Cells with Fin-Gate Leakage Control

The patent transitions from planar 2D memory cell structures to three-dimensional stacked structures. Multiple active layers are stacked vertically along a first direction, with word lines extending along a second direction and bit lines along a third direction perpendicular to both. This dimensional change allows increased cell density without proportionally increasing parasitic capacitance, as the vertical stacking efficiently utilizes space while maintaining controlled electrical characteristics through the triple-gate configuration.

The memory device is divided into multiple discrete active layers stacked vertically, with each layer having its own source and drain regions. The word lines are segmented to individually cover fin channel layers of respective active layers. This segmentation allows independent control and optimization of each layer's electrical characteristics, enabling better management of parasitic capacitance while achieving high density through vertical integration.

The patent implements a three-dimensional stacked architecture where active layers are stacked along a first direction, word lines extend along a second direction, and bit lines extend along a third direction. This vertical stacking approach dramatically increases cell density within the same footprint compared to planar structures, achieving higher capacity without proportionally increasing manufacturing complexity through systematic process integration.

The active layers serve multiple functions: they provide the channel region for transistor operation, form the basis for capacitor integration, and enable vertical stacking for high density. The word lines simultaneously provide gate control for respective active layers and contribute to the triple-gate structure that enhances current characteristics. This multi-functionality reduces the need for separate dedicated structures, managing complexity while achieving high performance.

The patent overcomes the area-density tradeoff by transitioning to vertical stacking. Multiple active layers are stacked along a first direction with word lines along a second direction and bit lines along a third direction. This three-dimensional configuration allows the memory device to achieve high net die density without further shrinking the planar area of individual cells, as density increases are achieved through the vertical dimension rather than lateral compression.

The patent implements a nested configuration where fin channel layers are covered by word line protrusions, creating a triple-gate structure. The word lines individually cover the fin channel layers of respective active layers, with bit lines connected to first ends and capacitors to second ends. This nested arrangement maximizes the use of available space by layering functional elements vertically, achieving high density without requiring further area reduction.