Stacked Memory Coprocessor Layout for Fast FPGA Reconfiguration
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Solution Overview
Problem
The speed of reconfiguration in programmable devices is significantly slower than desired in datacenter applications, and on-chip caching or buffering of configuration bit streams is costly in terms of silicon real estate and energy-intensive, especially when repeatedly fetching configuration data from off-chip storage.
Innovation Solution
A coprocessor integrated circuit (IC) die is used to accelerate functions by selecting pre-configured logic sectors and storing configuration data and intermediate results in vertically stacked memory IC dies within the same IC package, utilizing through-silicon vias (TSVs) for high-speed data transmission, allowing for efficient reconfiguration and parallel processing without interrupting operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If configuration data is stored in off-chip memory, then silicon real estate is saved, but reconfiguration speed becomes too slow for datacenter virtualization rates
Solution Approach 1:
The patent transitions from traditional planar integration to three-dimensional stacked architecture using through-silicon vias (TSVs). Configuration memory is stacked vertically above the coprocessor die, enabling high-speed data transmission via TSVs while maintaining compact footprint. This vertical dimension resolves the contradiction by providing fast reconfiguration access without consuming additional planar silicon area.
2Speed
If configuration data is cached in on-chip memory, then reconfiguration speed improves, but silicon real estate consumption increases undesirably
Solution Approach 1:
The patent employs vertical stacking with TSVs to place configuration memory directly above the coprocessor die. This three-dimensional arrangement provides on-chip caching capability with high reconfiguration speed while minimizing planar footprint, as the memory occupies the vertical dimension rather than consuming additional silicon area.
Solution Approach 2:
The configuration memory is nested within the same IC package as the coprocessor, with memory dies stacked vertically above the processing die. This nested arrangement enables fast on-chip access to configuration data without the penalty of increased planar footprint, resolving the speed-area tradeoff.
3Quantity of substance
If configuration bit streams are repeatedly fetched from off-chip storage, then memory capacity is sufficient, but energy consumption becomes excessive
Solution Approach 1:
The patent implements pre-fetching of configuration bit streams into the vertically stacked on-chip memory before they are needed for reconfiguration. This preliminary action eliminates repeated fetches from off-chip storage, significantly reducing energy consumption while maintaining sufficient memory capacity for multiple configuration sets.
Solution Approach 2:
By stacking configuration memory vertically above the coprocessor die and using TSVs for high-speed access, the system enables efficient on-chip caching of multiple configuration bit streams. This reduces the frequency of off-chip fetches and associated energy consumption, while the vertical architecture maintains compact footprint.
4Reliability
If the entire configuration circuit chain is used for fetching bit streams, then data integrity is maintained, but reconfiguration latency increases
Solution Approach 1:
The patent extracts the configuration data path from the traditional lengthy off-chip fetch route and places configuration memory directly in the IC package with TSV-based high-speed connections. This extraction creates a dedicated, short data path that maintains integrity through controlled signaling while dramatically reducing reconfiguration latency by eliminating traversal through the entire configuration circuit chain.
Data Source
AI summary
An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.