3D Stacked Memory Repair via Integrated Fuse Programming
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Solution Overview
Problem
The existing semiconductor memory devices with stacked structures face challenges in efficiently repairing defective memory cells due to the high cost and time required for programming addresses in fuse circuits, as each memory chip must be accessed separately for address programming.
Innovation Solution
A semiconductor memory device with a 3D stacked structure that includes a repair chip with fuse circuits to program addresses for defective cells across multiple memory chips simultaneously, allowing for a simplified and cost-effective repair process by testing and programming all fuse circuits in one step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory chip is accessed separately for address programming in fuse circuits, then the repair process can be completed, but the manufacturing cost and time increase significantly
Solution Approach 1:
The patent combines multiple fuse circuits from different memory chips into a single integrated fuse circuit structure. This allows simultaneous programming of all fuse circuits in one operation rather than accessing each memory chip separately, thereby resolving the contradiction between repair capability and programming efficiency.
Solution Approach 2:
The integrated fuse circuit is designed to serve multiple memory chips simultaneously, making it a universal repair mechanism that can program addresses for defective cells across all stacked memory chips through a single programming operation, improving productivity while maintaining repair reliability.
2Ease of repair
If separate access to each memory chip is performed for fuse programming, then individual chip repair is achieved, but the overall manufacturing process becomes complex and time-consuming
Solution Approach 1:
By merging the fuse circuits of multiple memory chips into a single integrated structure, the patent simplifies the programming process from multiple separate operations to one unified operation, reducing process complexity while maintaining the ability to repair defective cells in each chip.
Solution Approach 2:
The integrated fuse circuit maintains logical segmentation for each memory chip's address space while physically combining the programming mechanism, allowing simple unified programming without complex individual chip access procedures.
3Productivity
If multiple memory chips are stacked vertically to increase capacity, then integration degree improves, but the repair process requires accessing each chip separately increasing cost and time
Solution Approach 1:
The patent merges the fuse programming capability across all stacked memory chips into a single integrated fuse circuit, enabling simultaneous programming of all chips in the stack. This resolves the contradiction by allowing high integration度 while eliminating the need for separate access to each chip, thereby reducing programming time and cost.
Data Source
AI summary
A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.