Stacked Semiconductor Memory With Optical And Electrical Fuse Segmentation
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently replacing defective memory cells post-packaging due to the limitations of optical fuses, which cannot be restored and require additional electrical fuses, leading to increased die size and interference with initialization operations.
Innovation Solution
A semiconductor device architecture that stacks core chips with optical fuses and an interface chip with electrical fuses, where information from the electrical fuses is transferred through through electrodes, eliminating the need for electrical fuses on the core chips and preventing startup time increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both optical fuses and electrical fuses are provided in a single chip, then both pre-packaging and post-packaging defective addresses can be repaired, but the die size increases
Solution Approach 1:
The invention divides the repair function into two separate chips: the first chip (memory chip) contains optical fuses for pre-packaging defect repair, while the second chip (control chip) contains electrical fuses for post-packaging defect repair. This segmentation allows each chip to have a specialized repair mechanism, avoiding the need to accommodate both fuse types on a single chip and thus preventing die size increase.
Solution Approach 2:
The invention introduces an intermediary mechanism where the second chip stores defective address information and transfers it to the first chip through internal wirings. This mediator approach allows the electrical fuse information to be communicated without requiring direct integration of both fuse types on the same chip, resolving the space constraint while maintaining comprehensive repair capability.
2Reliability
If defective addresses are loaded through external terminals, then post-packaging defects can be repaired, but the initialization operation between memory controller and memory module is interfered with and startup time increases
Solution Approach 1:
The invention extracts the electrical fuse information storage and transfer function from the external terminal interface and relocates it to the internal wiring system between chips. By taking out the defect address loading operation from the external communication path, the initialization operation between memory controller and memory module is no longer interfered with, and startup time is reduced.
Solution Approach 2:
The second chip (control chip) preliminarily stores the defective address information in its electrical fuses before the memory module starts up. This preliminary action allows the defect information to be ready for transfer through internal wirings before external initialization operations begin, avoiding interference and reducing startup time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient replacement of defective memory cells without increasing the core chip area and prevents interference with initialization operations, ensuring reliable and efficient semiconductor device startup.
Implementation Method 1
Optical fuses are fuses that can be blown by irradiation of a laser beam or the like
Implementation Method 2
a plurality of internal wirings connected between the first chips and the second chip, each of the internal wirings including a plurality of through electrodes, each of the through electrodes penetrating through a corresponding one of the first chips
Data Source
AI summary
A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.