Vertically Stacked Memory Cells With GaP Channels for High Density

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Solution Overview

Problem

Current memory arrays face challenges in efficiently utilizing channel materials with large bandgaps for vertically-stacked memory cells, particularly in maintaining charge carrier mobility and compatibility with silicon lattices.

Innovation Solution

Incorporating gallium phosphide (GaP) as the channel material in transistors of vertically-stacked memory cells, which provides a large bandgap and reasonable charge carrier mobility, along with suitable conductive and dielectric materials, to enhance memory cell performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If vertically-stacked memory cells are used to increase storage density, then the quantity of memory cells per unit area increases, but charge carrier mobility deteriorates due to material compatibility issues

Engineering Contradiction:
Improvememory cell densityVSAvoidcharge carrier mobility
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent changes the material parameter of the channel from conventional silicon to gallium phosphide (GaP), which has a larger bandgap. This parameter change enables vertically-stacked memory cells to maintain stable electrical characteristics and acceptable charge carrier mobility while achieving higher storage density through vertical stacking.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures by integrating GaP channel layers with silicon lattice substrates. This composite approach combines the advantages of GaP (large bandgap for stability) with silicon's成熟的 fabrication processes, resolving the contradiction between vertical stacking density and charge carrier mobility.

Inventive Principle:
Principle #40Composite materials

2Reliability

If channel materials with large bandgaps are used to improve stability, then the reliability of memory cells improves, but compatibility with silicon lattices deteriorates

Engineering Contradiction:
Improvememory cell stabilityVSAvoidsilicon lattice compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent selects GaP as the channel material, changing the material parameter to achieve a larger bandgap. This improves memory cell stability and reliability while maintaining compatibility with silicon lattice fabrication processes through established semiconductor manufacturing techniques.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of GaP channel material in memory cells improves the efficiency and compatibility of memory arrays by maintaining charge carrier mobility and compatibility with silicon lattices, leading to improved data storage and retrieval capabilities.

Implementation Method 1

Incorporating gallium phosphide (GaP) as the channel material in transistors of vertically-stacked memory cells, which provides a large bandgap and reasonable charge carrier mobility

Methodology Applied
Scientific EffectCharge carrier mobility: Conduction (electrical)

Implementation Method 2

The capacitor may electrostatically store energy as an electric field within capacitor dielectric between two capacitor plates

Methodology Applied
Scientific EffectElectrostatic energy storage: Capacitance

Data Source

PatentEP3673510B1Memory arrays comprising memory cells
Publication Date: 2024.09.25 MICRON TECHNOLOGY INC
  • EP3673510B1 patent drawingFigure 1
  • EP3673510B1 patent drawingFigure 2~2A
  • EP3673510B1 patent drawingFigure 3

AI summary

Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.