Stacked Memory Gate Control for Tunneling Suppression
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Solution Overview
Problem
The collectively-processed lamination method for semiconductor memory devices faces challenges in suppressing band-to-band tunneling during write operations and accelerating tunneling during erase operations, leading to potential miswriting due to high leak currents and insufficient hole current generation.
Innovation Solution
The semiconductor memory device employs a structure with first and second select transistors, memory cell transistors, and dummy transistors, where specific potentials are applied to the gate electrodes of these transistors to control the write operation, reducing leak currents and enhancing hole current generation for efficient data writing and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the collectively-processed lamination method is used to form memory structures with stacked transistors, then the number of lithography processes remains independent of the number of laminations, but band-to-band tunneling occurs during write operations causing high leak currents and potential miswriting
Solution Approach 1:
The gate electrode structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation allows selective application of potentials to different regions, enabling suppression of band-to-band tunneling in specific areas while maintaining memory write operations in other areas, thus resolving the contradiction between manufacturing ease and data writing accuracy.
Solution Approach 2:
Different potential values are applied to different gate electrodes based on their local functional requirements. The first gate electrode receives a first potential value to suppress tunneling, while the second and third gate electrodes receive different potential values to enable or disable memory cell operations. This local differentiation of electrical properties allows simultaneous achievement of low leak currents and reliable data writing.
2Speed
If higher potential difference is applied between select gates and source/bit lines to accelerate hole current generation during erase operations, then erase speed improves, but band-to-band tunneling is also enhanced causing increased leak currents during write operations
Solution Approach 1:
The gate control structure is divided into multiple independently controllable gate electrodes that can be selectively activated. During write operations, specific gate electrodes are controlled to suppress tunneling and reduce leak currents, while during erase operations, different gate electrode combinations are activated to accelerate hole current generation. This temporal and spatial segmentation of gate control enables independent optimization of write and erase operations.
Solution Approach 2:
The potential values applied to different gate electrodes are dynamically adjusted based on the operation mode (write, erase, or read). The control circuitry changes the electrical state of different gate electrodes according to the required operation, enabling the system to optimize performance for each specific operation while minimizing adverse effects.
3Speed
If the silicon body potential is not maintained during write operations, then write speed improves, but miswriting occurs due to insufficient suppression of band-to-band tunneling
Solution Approach 1:
The gate electrode system is segmented into multiple independently controlled units that can selectively suppress band-to-band tunneling in specific regions while allowing fast write operations in other regions. This spatial segmentation enables simultaneous achievement of high write speed and high data writing accuracy by controlling tunneling suppression locally rather than globally.
Solution Approach 2:
Different potential values are applied to different gate electrodes based on local operational requirements. In regions where data writing is正在进行, potentials are configured to enable fast writing, while in regions where tunneling suppression is critical, different potentials are applied to prevent miswriting. This local optimization resolves the contradiction between speed and accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses leak currents during write operations and accelerates hole current generation during erase operations, preventing miswriting and ensuring accurate data storage by maintaining the silicon body potential, thereby improving the overall performance of the memory device.
Implementation Method 1
The potential Vsg of select gates is set to a potential value that satisfies Verase>Vsg. The silicon body potential Vbody is raised by a hole current generated by band-to-band tunneling due to a potential difference between the select gates and the source lines or bit lines, thereby erasing data.
Implementation Method 2
The potential Vbody of the silicon bodies is raised by the coupling of the word lines boosted to Vpass, the upper select transistors go into an off state due to a back gate effect, and the silicon body potential Vbody is thus maintained.
Data Source
AI summary
A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.