3D Semiconductor Memory Layout for Dense Stacking With Fewer Process Steps
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Solution Overview
Problem
As semiconductor memory devices undergo high integration, existing technologies face challenges in efficiently manufacturing three-dimensional configurations that maintain high performance and integration without increasing the number of manufacturing processes.
Innovation Solution
The semiconductor memory device employs a configuration with multiple memory portions, semiconductor layers, gate electrodes, a gate insulating film, and wiring structures arranged in specific directions, allowing for high integration and efficient manufacturing while maintaining large ON current and performance stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memory devices are converted into three-dimensional form to achieve high integration, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional stacked structures by forming semiconductor layers and gate electrodes in multiple tiers vertically. Multiple memory portions are stacked in the thickness direction, enabling higher integration density while maintaining manufacturability through systematic formation processes for each layer.
Solution Approach 2:
The memory device is divided into multiple independent memory portions (first memory portion, second memory portion, etc.) that are stacked vertically. Each memory portion contains complete functional elements (semiconductor layers, gate electrodes, insulating films, wirings) that can be formed through repeated application of the same manufacturing processes, segmenting the complex 3D structure into manageable repeating units.
2Quantity of substance
If multiple semiconductor layers and gate electrodes are stacked to improve integration, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Gate insulating films are formed on the surfaces of semiconductor layers before gate electrodes are formed. This preliminary formation of insulating layers establishes precise spacing and alignment references that guide subsequent electrode formation, ensuring consistent positioning across multiple stacked layers without requiring ultra-precise direct alignment.
Solution Approach 2:
Gate insulating films serve as intermediary layers between semiconductor layers and gate electrodes, and between adjacent semiconductor layers. These insulating films provide physical spacing and electrical isolation, allowing layers to be formed with standard precision while maintaining the required structural relationships through the mediating presence of the insulating material.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory portions arranged in a first direction, a plurality of semiconductor layers arranged in the first direction and electrically connected to the plurality of memory portions respectively, a plurality of gate electrodes arranged in the first direction and opposed to the plurality of semiconductor layers respectively, a gate insulating film disposed between the plurality of semiconductor layers and the plurality of gate electrodes, a first wiring extending in the first direction and connected to the plurality of gate electrodes, and a plurality of second wirings arranged in the first direction and connected to the plurality of semiconductor layers respectively. The plurality of semiconductor layers are opposed to surfaces on one side and the other side of each of the plurality of gate electrodes in the first direction via the gate insulating film.