Stacked Nonvolatile Memory Ground Transistors Structural Integrity
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Solution Overview
Problem
The challenge in developing three-dimensional nonvolatile memory devices is to ensure structural integrity, particularly in stacked configurations where features are formed on air gaps, which can weaken the structure and affect the reliability of the devices.
Innovation Solution
The implementation of a nonvolatile memory device design that includes a memory cell array with a block gating unit, address decoder, and ground transistors with channels extending perpendicular to the direction of metal lines, which improves the structural integrity and reliability by effectively connecting and disconnecting metal lines to selected and unselected memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional stacked array to improve integration density, then the integration density is improved, but the structural integrity deteriorates due to features being formed on air gaps
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell arrangement to a three-dimensional stacked configuration. Multiple memory cell layers are stacked vertically, with each layer containing memory cells arranged in rows and columns. This vertical stacking enables significantly higher integration density by utilizing the third dimension (height) for additional memory storage capacity.
Solution Approach 2:
The patent introduces ground transistors as intermediary elements between the memory cell layers and the substrate. These ground transistors provide structural support and electrical grounding to the stacked memory cell structures, helping to stabilize the three-dimensional configuration and mitigate structural integrity issues arising from air gaps between stacked layers.
2Strength
If ground transistors are configured with channels extending perpendicular to metal lines, then the structural integrity is improved, but the device complexity increases
Solution Approach 1:
The patent applies different channel orientations to different transistor types within the same memory device. Specifically, ground transistors have their channels extending in a first direction (perpendicular to metal lines), while string selection transistors have their channels extending in a second direction (parallel to metal lines). This localized differentiation optimizes each transistor type for its specific function while maintaining overall device performance.
Solution Approach 2:
The patent segments the transistor population into distinct groups with different configurations based on their functional roles. Ground transistors are separated from string selection transistors, with each group having optimized channel orientations. This segmentation allows each transistor type to be independently optimized for its specific function without compromising the other.
Data Source
AI summary
A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.