Vertically Stacked Memory Package for HBM Bandwidth Bottlenecks
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Solution Overview
Problem
Conventional High Bandwidth Memory (HBM) solutions face limitations in bandwidth due to a limited number of channels between the HBM and processor, lack of customization options, and high costs, making it challenging to meet increasing data storage demands in electronic devices.
Innovation Solution
A memory device is stacked vertically with a processing device using a substrate with multiple memory units and conductive interconnects, eliminating the need for an interposer or package substrate, and allowing for scalable memory size through wafer bonding, enabling increased bandwidth and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HBM is positioned laterally to processor with interposer, then bandwidth is increased up to 3 times compared to unstacked DRAM, but bandwidth is still limited by bottleneck due to limited maximum number of channels between HBM and processor
Solution Approach 1:
The patent transitions from lateral positioning of HBM to the processor to vertical stacking, changing the spatial dimension of interconnection. This vertical stacking enables significantly increased bandwidth by providing more interconnect channels without the bottleneck limitations of lateral arrangements, while eliminating the need for complex interposer structures.
Solution Approach 2:
The patent removes the interposer component from the system architecture. By eliminating the interposer, the design simplifies the interconnection structure between HBM and processor, reducing device complexity while maintaining or improving bandwidth through direct vertical stacking and increased interconnect channels.
2Quantity of substance
If more DRAM die is stacked/unstacked in HBM, then memory size increases/decreases, but there is no way to customize the memory size the HBM provides and cost and availability become issues
Solution Approach 1:
The patent divides the memory system into modular DRAM die units that can be independently stacked in various configurations. This segmentation enables customization of memory size by selecting different numbers and combinations of DRAM die, allowing the system to be tailored to specific application requirements while maintaining cost-effectiveness through standardized modular components.
Solution Approach 2:
The patent enables dynamic configuration of memory capacity through vertical stacking of DRAM die, where the memory size can be adjusted by changing the number of stacked die. This dynamic adaptability allows customization of memory capacity to match different application needs without being locked into fixed configurations, improving versatility while managing cost and availability.
3Productivity
If conventional HBM structure with interposer is used, then bandwidth is limited, but removing interposer and using vertical stacking increases bandwidth potential up to a thousand times greater bandwidth density
Solution Approach 1:
The patent implements vertical stacking of memory devices onto the processor, transitioning from lateral to vertical integration. This dimensional change enables dramatically increased bandwidth density by maximizing the number of interconnect channels within a compact footprint, achieving up to a thousand times greater bandwidth density while simplifying the overall system architecture by eliminating the interposer.
Data Source
AI summary
A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.