Stacked Memory Chip Structure With Heat-Conduction Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the stacking of chip units for memory devices, poor welding due to uneven heat conduction rates between chip units leads to low product yield, as the heat conduction rates of different chip units and their regions can vary significantly, causing inconsistent welding temperatures.
Innovation Solution
A semiconductor structure with a heat conduction adjusting layer is introduced, which is in contact with the substrates to reduce the difference in heat conduction rates between surfaces, ensuring consistent temperatures during the thermal compression bond process and improving the welding quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chip units are stacked by thermal compression bond to improve storage capacity, then the storage capacity increases, but poor welding occurs due to uneven heat conduction rates between chip units
Solution Approach 1:
The patent applies local quality by introducing a heat conduction adjusting layer with specific heat conduction characteristics at the bonding interface between chip units. This layer has different heat conduction properties than the surrounding materials, specifically designed to compensate for the uneven heat conduction rates of different chip units. By modifying the thermal properties locally at the bonding interface, the patent achieves uniform welding temperature across all chip units while maintaining high storage capacity through multi-chip stacking.
2Ease of manufacture
If thermal compression bond process is used to stack chip units, then the stacking process is simple, but inconsistent welding temperatures occur due to heat conduction rate differences
Solution Approach 1:
The heat conduction adjusting layer serves as an intermediary element between the chip units during the thermal compression bond process. This intermediate layer mediates the thermal interaction between chip units with different heat conduction rates, absorbing or distributing heat to achieve uniform welding temperature. The intermediary layer allows the simple thermal compression bond process to produce precise and consistent welding results without requiring complex process control.
3Adaptability or versatility
If chip units with different heat conduction rates are stacked, then various chip specifications can be integrated, but poor welding occurs due to temperature differences
Solution Approach 1:
The patent applies parameter changes by modifying the heat conduction parameter of the bonding interface through the heat conduction adjusting layer. This layer is specifically designed with heat conduction characteristics that compensate for variations in chip unit heat conduction rates. By adjusting the thermal parameter at the interface, the patent enables welding of chip units with different specifications and heat conduction properties while maintaining consistent welding quality and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The heat conduction adjusting layer reduces the probability of poor welding by equalizing heat conduction rates, thereby enhancing the product yield and storage capacity by ensuring reliable connections between chip units.
Implementation Method 1
a heat conduction adjusting layer, which is in contact with the substrates to reduce the difference in heat conduction rates between surfaces
Implementation Method 2
The chipset including the heat conduction adjusting layer is connected fixedly with the base by a thermal compression bond process
Data Source
AI summary
A semiconductor structure includes a base, a chipset and a heat conduction adjusting layer. The chipset is disposed at one side of the base and includes multiple chip units arranged at intervals along a direction perpendicular to the base. Each of the chip units includes a substrate and a circuit module disposed on a surface of the substrate. The substrate includes a circuit interconnection region and a non-circuit interconnection region distributed adjacently. The circuit module is disposed on a surface of the circuit interconnection region, and adjacent chip units are electrically connected by the circuit module. The heat conduction adjusting layer is in contact with at least one of the substrates for reducing the difference of heat conduction rates between surfaces of the substrates.