Stacked Memory Architecture for Heat Dissipation and Page Buffer Area
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Solution Overview
Problem
The challenge in the memory device industry is to effectively dissipate the heat generated during operation, especially as chip sizes shrink and operating speeds increase.
Innovation Solution
The proposed solution involves a memory device architecture where a peripheral substrate, an array substrate, and a high voltage processing substrate are stacked, with the high voltage processing circuit occupying less than 10% of the peripheral substrate area in some embodiments, allowing for more space for a larger page buffer and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the chip size is shrunk and operating speed is increased, then the data storage capacity and operating speed are improved, but the heat generation increases and thermal management becomes more difficult
Solution Approach 1:
The patent divides the memory device into multiple substrates (array substrate and peripheral substrate) stacked together, separating different functional circuits onto different substrates. This segmentation allows for better thermal management by distributing heat sources across multiple layers and enabling targeted thermal control for high-power components like the charge pump circuit.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture, placing the array substrate and peripheral substrate in different layers. This vertical stacking enables improved heat dissipation by exposing more surface area for thermal management and allowing heat to dissipate in multiple directions rather than being confined to a single plane.
2Device complexity
If the high voltage processing circuit is integrated on the peripheral substrate, then the device complexity is reduced, but the area available for page buffer is decreased
Solution Approach 1:
The patent segments the high voltage processing circuit (charge pump) from the page buffer circuit, placing them on different substrates or separate regions. This segmentation allows the page buffer to occupy more area on the peripheral substrate while maintaining full functionality through the stacked architecture connection.
Solution Approach 2:
The patent introduces an intermediary connection structure (such as through-silicon vias or interlayer connectors) that enables communication between the array substrate and peripheral substrate. This intermediary allows the high voltage processing circuit to be separated from the page buffer while maintaining functional integration, effectively resolving the area conflict.
Data Source
AI summary
A memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuits and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a circuit distribution area of the high voltage processing circuit accounts for less than 10% of the peripheral substrate area.