Stacked Memory Cell Heating Electrode for Phase Transition

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Solution Overview

Problem

Current semiconductor technologies face challenges in achieving high integration of memory devices, particularly in developing variable-resistance memory devices with efficient heat transfer mechanisms for phase-change random access memory (PRAM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM) devices.

Innovation Solution

A semiconductor device with a stacked structure comprising cell structures that include a capping layer, a selection layer, a buffer layer, a variable resistance layer, and an upper electrode layer, where a heating electrode is strategically positioned between the variable resistance layer and the upper electrode to transfer heat, enabling efficient Joule heating and phase transitions in the variable resistance layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If memory devices are integrated horizontally in a planar arrangement, then device area utilization is improved, but integration density and scalability deteriorate

Engineering Contradiction:

Improvedevice area utilizationVSAvoidintegration density

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent transitions from planar horizontal integration to vertical three-dimensional stacking of memory cell structures. Multiple cell structures are stacked in the vertical direction (e.g., 32 layers) to achieve high integration density while maintaining efficient heat dissipation pathways to the substrate, thereby resolving the contradiction between area utilization and integration density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If high current is applied to the variable resistance layer for rapid phase transition, then switching speed is improved, but heat generation and energy loss worsen

Engineering Contradiction:

Improveswitching speedVSAvoidheat generation

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent introduces a heating electrode as an intermediary component positioned between the upper electrode layer and the variable resistance layer. This heating electrode efficiently transfers heat to the variable resistance layer, enabling rapid phase transitions with reduced energy loss compared to direct high current application, thus resolving the contradiction between switching speed and energy loss.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If vertical stacking of cell structures is implemented to increase integration, then integration density is improved, but heat dissipation efficiency deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoidheat dissipation efficiency

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The patent segments the memory device into multiple independent cell structures stacked vertically, each with its own variable resistance layer and electrode structures. This segmentation allows heat to be dissipated from each layer to the substrate through dedicated pathways, preventing heat accumulation and maintaining dissipation efficiency even with high integration density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The heating electrode serves as a thermal intermediary that efficiently transfers heat from the variable resistance layer to the upper electrode layer and subsequently to the substrate. This intermediary heat transfer mechanism ensures effective heat dissipation in the vertically stacked configuration, resolving the contradiction between integration density and heat dissipation efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for high integration of memory cells with efficient heat transfer, enabling the variable resistance layer to change resistance states effectively, thereby enhancing the performance of PRAM, MRAM, and ReRAM devices.

Implementation Method 1

a heating electrode between the variable resistance layer and the upper electrode layer, the heat electrode to transfer heat to the variable resistance layer

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

enabling efficient Joule heating and phase transitions in the variable resistance layer

Methodology Applied

Scientific EffectJoule heating: Joule Heating

Implementation Method 3

enabling efficient Joule heating and phase transitions in the variable resistance layer

Methodology Applied

Scientific EffectPhase transitions: Phase Change

Data Source

PatentUS10825986B2Semiconductor devices including a stacked cell structure

Publication Date: 2020.11.03 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.