Vertically stacked storage nodes and access devices with horizontal access lines
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Solution Overview
Problem
As design rules shrink, less semiconductor space is available for fabricating memory cells, leading to challenges in increasing memory array density and reducing contact resistance in DRAM arrays.
Innovation Solution
A vertically stacked three-dimensional memory architecture is implemented with horizontally oriented access devices and storage nodes, where storage nodes are vertically stacked between access devices, reducing the lateral footprint and improving charge storage capacity while utilizing materials with lower mobility to enhance contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are shrunk to increase memory array density, then memory array density is improved, but contact resistance increases
Solution Approach 1:
The patent transitions from a planar two-dimensional memory architecture to a three-dimensional vertically stacked architecture. Memory cells are arranged in multiple vertical layers with access devices stacked above storage nodes, allowing density improvement in the vertical dimension while maintaining manageable contact resistance through controlled vertical connections and material selection.
2Ease of manufacture
If conventional planar architecture is used, then fabrication is simpler, but memory array density is limited
Solution Approach 1:
The patent implements a three-dimensional vertically stacked memory architecture where access devices and storage nodes are positioned in different vertical layers. This dimensional transition enables significantly higher memory array density compared to conventional planar architectures while managing fabrication complexity through systematic layer formation processes.
Solution Approach 2:
The patent structures memory cells with storage nodes positioned below and access devices positioned above, creating a nested vertical configuration. Multiple memory cells are stacked vertically sharing common bit lines, enabling high density integration while maintaining relatively simple fabrication processes through sequential layer formation.
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Horizontally oriented access lines are coupled to gates, separated from the respective channel regions by gate dielectrics, and vertically oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.