Stacked Memory Chip Structure for Hydrogen Diffusion Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining high reliability and preventing negative-bias temperature instability (NBTI) in peripheral circuit transistors due to hydrogen diffusion from hydrogen-containing insulating layers, which affect the performance and integrity of the devices.
Innovation Solution
The semiconductor device incorporates a hydrogen-containing insulating layer positioned adjacent to the memory structure to supply hydrogen for defect curing while minimizing diffusion to peripheral circuit transistors, using specific positioning and annealing processes to control hydrogen distribution, thereby enhancing the reliability of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hydrogen-containing insulating layer is disposed adjacent to the memory structure to supply hydrogen for defect curing, then the reliability of the memory structure is improved, but hydrogen may diffuse to peripheral circuit transistors causing negative-bias temperature instability
Solution Approach 1:
The patent applies local quality by disposing the hydrogen-containing insulating layer specifically in the first chip structure adjacent to the memory structure, while excluding it from the second chip structure containing peripheral circuit transistors. This localized placement ensures hydrogen is supplied only where needed for defect curing without causing NBTI in peripheral circuits.
Solution Approach 2:
The patent segments the semiconductor device into two distinct chip structures: a first chip structure containing the memory structure with the hydrogen-containing insulating layer, and a second chip structure containing peripheral circuit transistors without this layer. This segmentation isolates the hydrogen supply function to only the memory structure region.
2Reliability
If the semiconductor device uses highly integrated and complex structures to meet high reliability and high speed requirements, then device performance is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into separate first and second chip structures with distinct functions and configurations. The first chip structure handles memory functions with hydrogen-containing insulating layer, while the second handles peripheral circuits without it, simplifying the overall design and manufacturing process.
Solution Approach 2:
The patent applies different structural configurations to different regions: the first chip structure has the hydrogen-containing insulating layer for memory reliability, while the second chip structure has a simplified configuration suitable for peripheral circuits, avoiding unnecessary complexity in each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively supplies hydrogen to memory structures to cure defects while reducing adverse effects on peripheral circuit transistors, improving the overall reliability and performance of the semiconductor device by maintaining low hydrogen content in critical components.
Implementation Method 1
hydrogen diffusion from hydrogen-containing insulating layers
Implementation Method 2
annealing processes to control hydrogen distribution
Data Source
AI summary
A semiconductor device includes a first chip structure; and a second chip structure on the first chip structure. The first chip structure includes a base substrate, a memory structure on the base substrate, a first substrate on the memory structure, first through-vias penetrating the first substrate, a first wiring structure disposed on the first substrate; first bonding pads on an upper surface of the first wiring structure, and a hydrogen-containing insulating layer disposed in a region adjacent to the memory structure in the first chip structure. The second chip structure includes a second substrate, peripheral circuit transistors and a lower wiring structure disposed on a lower surface of the second substrate; second bonding pads electrically connected to the lower wiring layer, and bonded to the first bonding pads, respectively; and an upper wiring structure.