Stacked Memory Structure With Insulating Patterns for Data Retention
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face challenges in increasing integration density and operational reliability due to limitations in stacking memory cells vertically over a substrate, leading to issues with charge movement and data retention between memory cells.
Innovation Solution
A semiconductor device with a stacked structure of insulating and conductive layers, a hard mask pattern, and insulating patterns that protrude further towards the channel structure than the hard mask pattern, with a memory layer filling the space between the insulating patterns, enhancing data retention and reducing interference between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration density, then storage capacity is improved, but interference between memory cells increases and data retention deteriorates
Solution Approach 1:
The patent divides the memory structure into discrete memory cell units separated by insulating patterns. Each memory cell is segmented with its own channel structure and memory layer, isolated from adjacent cells by insulating patterns that extend between the channel structures. This segmentation prevents charge interference between vertically stacked memory cells while maintaining high integration density.
Solution Approach 2:
The patent introduces insulating patterns as intermediary elements between adjacent memory cells. These insulating patterns extend between the channel structures of neighboring memory cells, acting as charge barriers that prevent charge leakage and interference. The insulating patterns serve as mediators that enable vertical stacking while maintaining data retention by blocking charge migration paths between cells.
2Reliability
If insulating patterns protrude farther towards the channel structure than the hard mask pattern, then interference between memory cells is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms the insulating patterns before forming the channel structures, allowing the insulating patterns to protrude between the channel structures without requiring additional post-processing steps. This preliminary formation of insulating patterns simplifies the manufacturing process compared to alternative approaches that would require complex etching or deposition steps after channel formation.
Solution Approach 2:
The patent extends the insulating patterns in the vertical dimension to protrude between the channel structures of adjacent memory cells. By utilizing the vertical dimension for the insulating pattern extension rather than only horizontal extension, the design achieves effective charge isolation without significantly increasing lateral footprint or requiring complex three-dimensional shaping operations.
3Reliability
If a memory layer fills the space between insulating patterns, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned formation of the memory layer within the spaces between insulating patterns. The memory layer is deposited conformally to fill the available space, and subsequent processing steps automatically define the final memory layer boundaries based on the insulating pattern geometry. This self-service approach reduces the need for high-precision lithographic patterning of the memory layer itself, as the insulating patterns serve as natural alignment references.
Data Source
AI summary
A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.