3D Stacked Memory Device With Insulating Spacers
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices face challenges in enhancing memory density due to limitations in the arrangement and spacing of conductive and semiconductor elements.
Innovation Solution
The memory device incorporates a specific configuration of conductive and semiconductor layers with charge storage members and insulating layers, arranged in a manner that allows for improved packing density by optimizing the spacing and arrangement of these elements, enabling a more efficient use of space within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive layers and semiconductor members are arranged with sufficient spacing for manufacturing and electrical isolation, then device reliability is maintained, but memory density deteriorates due to increased space occupation
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked configuration, where conductive layers are arranged in multiple levels (first conductive layer, second conductive layer) with semiconductor members extending vertically. This vertical stacking enables memory cells to be packed in the third dimension while maintaining necessary horizontal spacing for manufacturing and electrical isolation, thereby increasing memory density without compromising device reliability
Solution Approach 2:
The patent implements nested structures where semiconductor members are positioned within regions defined by conductive layers and insulating members. The first semiconductor member extends between the first and second conductive layers, while the second semiconductor member is positioned adjacent to it, creating a compact nested arrangement that maximizes space utilization while preserving electrical isolation and manufacturing accessibility
2Quantity of substance
If conductive layers are positioned closer together to reduce device footprint, then memory density improves, but manufacturing precision requirements worsen due to tighter tolerances
Solution Approach 1:
The patent introduces insulating members as intermediary elements positioned between conductive layers and semiconductor members. These insulating members serve as spacers that define and maintain precise spacing relationships, making it easier to control distances between conductive layers and semiconductor members during manufacturing. The insulating members act as physical references that simplify the achievement of tight tolerances without directly increasing the device footprint
Solution Approach 2:
The patent divides the memory device into distinct functional segments: conductive layers for electrical connection, semiconductor members for active functions, and insulating members for isolation and spacing. This segmentation allows each component to be optimized and manufactured separately with standard precision, then assembled into a compact three-dimensional structure, reducing the overall manufacturing precision requirements compared to monolithic designs
Data Source
AI summary
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.