Stacked Semiconductor Memory Device Integration Density
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to high costs associated with forming fine patterns, prompting the need for three-dimensional semiconductor devices with increased density.
Innovation Solution
A semiconductor memory device design featuring a stacked configuration with multiple bit lines and word lines, where lower and upper memory cells are electrically connected to bit lines with varying distances between the bit lines and their respective gates, allowing for improved integration density and reduced bit line length, thereby enhancing integration density and signal transmission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used to increase integration density, then manufacturing cost increases due to expensive fine pattern equipment, but integration density is still restricted
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory cells arranged in multiple layers (first and second memory cell layers). This dimensional change allows integration density to increase without requiring finer patterns on the same plane, thereby avoiding the need for expensive fine pattern equipment while achieving higher density through vertical stacking of memory cells and bit lines
2Manufacturing precision
If bit line length is increased to connect more memory cells, then integration density improves, but signal transmission characteristics deteriorate due to increased bit line capacitance
Solution Approach 1:
The patent stacks memory cells and bit lines in three dimensions with bit lines arranged in first and second layers at different heights. This vertical stacking reduces the planar footprint and allows memory cells to be connected to bit lines with shorter lengths, thereby maintaining signal transmission characteristics while achieving higher integration density through the third dimension
Solution Approach 2:
The patent divides the bit line system into multiple segments across different layers (first bit line layer and second bit line layer), with each layer serving specific memory cell groups. This segmentation allows each bit line segment to be shorter, reducing individual capacitance values and improving signal transmission while the overall system achieves high density through the distributed layered structure
Data Source
AI summary
A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.