Stacked Memory Interface Layout for High-Capacity Low-Latency Access
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Solution Overview
Problem
Existing memory systems face challenges in increasing capacity while maintaining low latency and efficiency, particularly in applications requiring intensive operations such as graphics performance and artificial intelligence, due to the complexity of interface components and increased size.
Innovation Solution
A memory interface block is introduced that pairs controllers for at least two memory devices, sharing a command port and utilizing synchronous host interfaces with asynchronous device interfaces, enabling efficient stacking through through-silicon-vias to reduce latency and increase capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to support intensive operations, then storage capability is improved, but latency increases and efficiency deteriorates
Solution Approach 1:
The memory system is divided into multiple independent memory devices (e.g., 16 memory devices) that can be accessed simultaneously through parallel interfaces. Each memory device operates independently with its own command and data paths, allowing concurrent memory operations that reduce overall latency while maintaining high capacity.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory expansion to three-dimensional stacked architecture using through-silicon vias (TSVs). This vertical stacking enables multiple memory devices to be interconnected in the third dimension, increasing capacity without proportionally increasing footprint or access latency.
2Quantity of substance
If memory system size is increased to increase capacity, then storage capability is improved, but interface complexity increases
Solution Approach 1:
A single memory interface block is designed to control multiple memory devices (e.g., up to 16 devices) through a unified interface architecture. The interface block contains universal control logic that can manage command queues, data buffers, and timing for all connected memory devices, reducing the need for separate interface circuits for each device.
Solution Approach 2:
Multiple command ports and data interfaces are merged into a single integrated memory interface block. The interface block combines command decoding, address generation, data buffering, and error correction functions into one unified structure that serves all memory devices, simplifying the overall system architecture.
Data Source
AI summary
Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.