Stacked Memory Die Interface Split for Lower DRAM Power
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Solution Overview
Problem
The increasing demand for higher performance and capacity in DRAM devices leads to significant power consumption challenges, making it difficult to advance signaling rate and capacity while conventional DRAM fabrication processes compromise on efficiency due to inefficient high-speed logic circuitry.
Innovation Solution
A multi-die memory device architecture is introduced, where high-speed interface and core storage functions are split between separate integrated circuit dice, with the interface die fabricated using a process for power-efficient high-speed circuitry and the storage die using a process that balances cell retention time and storage density, allowing for shorter bit lines and reduced access power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM devices increase storage capacity and signaling bandwidth to meet higher performance demands, then device capacity and speed are improved, but power consumption increases dramatically
Solution Approach 1:
The patent segments the DRAM device into multiple separate memory dies, each with its own I/O circuitry. This allows independent optimization of each die's power consumption characteristics while collectively achieving higher storage capacity. Each die can be independently controlled and powered, enabling granular power management that prevents proportional power increase with capacity scaling.
2Productivity
If conventional DRAM fabrication processes are used to increase capacity, then storage density is improved, but efficiency deteriorates due to compromised high-speed logic circuitry
Solution Approach 1:
The patent divides the memory system into multiple independent dies that can be fabricated using conventional processes. Each die maintains efficient high-speed logic circuitry independently, avoiding the compromises that occur when trying to optimize entire high-capacity devices in single fabrication runs. This segmentation allows conventional fabrication processes to produce efficient individual dies without the complexity and efficiency losses of monolithic high-capacity device fabrication.
3Productivity
If multiple memory dies are used to increase storage capacity, then capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple independent memory dies into a unified memory system with coordinated I/O operations. The dies are combined in a way that presents a simplified interface to external systems while maintaining independent internal optimization. This merging approach achieves high storage capacity without proportionally increasing the complexity of the external interface and control logic.
Data Source
AI summary
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.